QDFLD25
‐
xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 11 -
Table 13: Read/Write Timing Specifications, PIO Mode 0-4
PIO timing parameters
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
t
0
Cycle time (min.)
600
383
240
180
120
t
1
Address valid to HIOR-/HIOW- setup (min.)
70
50
30
30
25
t
2
HIOR-/HIOW- 16-bit (min.)
165
125
100
80
70
t
2
HIOR-/HIOW- Register 8-bit (min.)
290
290
290
80
70
t
2i
HIOR-/HIOW- recovery time (min.)
-
-
-
70
25
t
3
HIOW- data setup (min.)
60
45
30
30
20
t
4
HIOW- data hold (min.)
30
20
15
10
10
t
5
HIOR- data setup (min.)
50
35
20
20
20
t
6
HIOR-
data
hold
(min.)
5 5 5 5 5
t
6z
HIOR- data tri-state (max.)
30
30
30
30
30
t
7
Address valid to IOCS16- assertion (max.)
90
50
40
n/a
n/a
t
8
Address valid to IOCS16- released (max.)
60
45
30
n/a
n/a
t
9
HIOR-/HIOW- to address valid hold
20
15
10
10
10
t
RD
Read data valid to IORDY active (min.)
0
0
0
0
0
t
A
IORDY setup time
35
35
35
35
35
t
B
IORDY pulse width (max.)
1250
1250
1250
1250
1250
t
C
IORDY
assertion
to
release
(max.)
5 5 5 5 5
Multiword DMA
Figure 5: Read/Write Timing Diagram, Multiword DMA Mode
