QDFLD25
‐
xxx(M/G)UH1(I)
Datasheet
80000-FLD25-xxx(M/G)UH1(I)-March2011
- 7 -
3. Interface
Description
3.1. Physical Description
The pin 1 ~ pin 44 are for IDE interface. The pin A ~ pin D are for option selection via physical jumpers.
Figure 3: The front view of 2.5” PATA (IDE) SSD 44-pin IDE Connector
3.2. Pin Assignments
Signals whose source is the host is designated as inputs while signals that the Industrial 44-pin micro IDE Flash (2.5”
PATA (IDE) SSD) Disk sources are outputs. The pin assignments are listed in below table 7.
Table 7: Pin Assignments
Pin No.
Signal Name
Description
Pin No.
Pin Name
Description
1 HRESET
Host
Reset
2
GND Ground
3
HDB[7]
Host Data Bit 7
4
HDB[8] Host
Data
Bit
8
5
HDB[6]
Host Data Bit 6
6
HDB[9] Host
Data
Bit
9
7
HDB[5]
Host Data Bit 5
8
HDB[10] Host
Data
Bit
10
9
HDB[4]
Host Data Bit 4
10
HDB[11] Host
Data
Bit
11
11
HDB[3]
Host Data Bit 3
12
HDB[12] Host
Data
Bit
12
13
HDB[2]
Host Data Bit 2
14
HDB[13] Host
Data
Bit
13
15
HDB[1]
Host Data Bit 1
16
HDB[14] Host
Data
Bit
14
17
HDB[0]
Host Data Bit 0
18
HDB[15] Host
Data
Bit
15
19
GND Ground
20
KEY
1
Key-pin
21
DMARQ DMA
Request
22
GND Ground
23
HIOW
3
Host
I/O
Write
24
24 GND
STOP
4
Stop Ultra DMA burst
25
HIOR
3
Host
I/O
Read
26 GND
Ground
HDMARDY
4
Ultra DMA ready
HSTROBE
4
Ultra DMA data strobe
27
IORDY
3
I/O
Ready
28 CSEL
Cable
select
DDMARDY
4
Ultra DMA ready
DSTROBE
4
Ultra DMA data strobe
