AWARD BIOS Description
4 - 8
•
EDO RAS#
Precharge Time
3
DRAM RAS# Precharge time=3x system clocks.
4
DRAM RAS# Precharge time=4x system clocks.
•
EDO DRAM Read
Burst
×
3 3 3,
×
2 2 2,
The DRAM read burst timing depends on the type
of DRAM on a per-row basis. Slower rates may be
required to support slower DRAM.
•
EDO DRAM Write
Burst
×
2 2 2,
×
3 3 3,
The DRAM write burst timing depends on the type
of DRAM on a per-row basis. Slower rates may be
required to support slower DRAM.
•
DRAM Data Integrity
Mode
ECC
Provide ECC (Error Checking and Correction)
function.
Non-ECC
Disable ECC / EC function.
•
CPU-To-PCI
IDE Posting
Enabled
Disabled
Enable CPU-To-PCI write posting.
Disable CPU-To-PCI write cycles to IDE.
•
System BIOS
Cacheable
Enabled
Beside conventional memory, the system BIOS
area is also cacheable.
Disabled
The system BIOS area is not cacheable.
•
Video BIOS
Cacheable
Enabled
Disabled
Beside conventional memory, video BIOS area is
also cacheable.
Video BIOS area is not cacheable.
•
Video RAM
Cacheable
Enabled
Beside conventional memory, video BIOS area is
also cacheable.
Disabled
Video BIOS area is not cacheable.
•
8 Bit I/ O Recovery
Time
1
∼
8
Define the ISA Bus 8 bit I/O operating recovery
time.
NA
8 bit I/O recovery time is not exist.
•
16 Bit I / O
Recovery Time
1
∼
4
Define the ISA Bus 16 bit I/O operating recovery
time.
NA
16 bit I/O recovery time is not exist.
•
Memory Hole At
15M-16M
Enabled
Memory Hole at 15-16M is reserved for expanded
PCI card.
Disabled
Do not set this memory hole.
•
Delayed
Transaction
•
AGP Aperture Size
(MB)
4
∼
256
Set the effective size of the Graphics Aperture to be
used in the particular PAC Configuration.
•
SDRAM RAS-To-
CAS Delay
Fast
Slow
RAS-To-CAS Delay time=2 HCLK
RAS-To-CAS Delay time=3 HCLK
•
SDRAM RAS
Precharge Time
Fast
Slow
RAS Precharge Time=2 HCLK
RAS Precharge Time=3 HCLK
•
SDRAM CAS Latency
Time
Fast
Slow
Define the CLT timing parameter of SDRAM
expressed in 66 MHz clocks. Latency Time=2
clocks
Latency Time=3 clocks
Power Management Setup
