Introduction
13
Pulse sequence:
Multiple pulse producing mode where 1-250 pulse points are
produced in sequence. Gate delay, width, Delayed Trigger Out, and Aux Del’d
Trig Out can be varied. Gate width must remain within 1 of 3 ranges: < 15 nsec,
15-199 nsec, > 15 nsec during sequence. Maximum pulse rate = 1.9 kHz.
Gate pulse width:
3.5 nsec to 80 msec continuously adjustable in 1 nsec increments,
except below 15 nsec where it is adjustable in 2 nsec increments. Gate delay +
gate width cannot exceed 80 msec total. Width is measured FWHM (Full width
at half maximum amplitude).
DELAYED TRIGGER OUT pulse:
Initially synchronized to trailing edge of high
voltage gate pulse, i.e. delayed from trailing edge of gate pulse by 20 µsec. Sync
delay can be varied from 1-100 µsec. Delays can also be programmed from input
trigger in 1 nsec increments, 200 nsec – 80 msec.
5 V negative logic BNC output, modifiable to 5 V/15 V negative or positive
logic, peak power = 0.5W, peak current 1.5A typical, width >1 µsec, rise/fall
times < 7 nsec.
AUX DLY’D TRIG OUT:
Initially synchronized to trailing edge of high voltage gate
pulse, i.e. delayed from trailing edge of gate pulse by 20 µsec. Sync delay can be
varied from 1-100 µsec. Delays can be programmed from input trigger in 80 nsec
(±80 nsec accuracy) increments, 1 µsec – 80 msec. TTL compatible (HC series
TTL) 5 V negative logic BNC output, modifiable to 5 V positive, width >1 µsec,
rise/fall times < 7 nsec.
Pulse monitor:
Gate pulse timing reference with an approximate amplitude of –2 volts
(100:1 ratio capacitive divider). For longer gate widths, the pulse monitor may
appear to be differentiated. However, the vertical edges of the pulse monitor still
accurately represent the leading and trailing edges of the gate pulse.
External trigger input, electrical:
5 nsec minimum pulse width, BNC connector,
±10 V range, 40 mV sensitivity, 50/2000
impedance, AC/DC coupling, 2 W
maximum power into 50
, ±20 volts maximum voltage (both conditions must
be satisfied).
Manual external trigger inputs can be simulated by polarity switch toggling
although extra triggers will probably be generated due to switching noise.
External trigger input, optical:
5 nsec minimum pulse, SMA connector, 400-1150
nm, 0.5 A/W at 850 nm. Required settings: 50
trigger impedance, trigger
polarity negative, trigger level < 0 V, e.g., –1 V.
INHIBIT/
INHIBIT
inputs: TTL compatible; ±15 volts maximum voltage, < 50 nsec
internal delay. Without connections the PG-200 is always enabled.
INHIBIT
is a negative logic INHIBIT input.
Dual gate pulses:
Gate delay skew:
at 3-14 nsec widths:
2 nsec
at 15-199 nsec widths:
5 nsec
at 200+ nsec widths:
10 nsec or 0.1%, whichever is greater
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