Introduction
ROBO-603 User’s Manual
1-6
1.4.1 VIA
VT82C694X
The VIA VT82C694X along with the VT82C686A companion chip provide the basic functionality
and buses of the system:
High Performance CPU interface.
Full Featured Accelerated Graphics Port (AGP) controller.
Advanced High-Performance DRAM controller. PC133 compliant SDRAM must be used if
133MHz FSB CPU is to be used.
Concurrent PCI Bus controller.
PCI to ISA Bridge provided by VT82C686A super south bridge.
Universal Serial Bus controller integrated in the VT82C686A.
UltraDMA-33 / 66 Master Mode PCI EIDE controller. Two connectors are provided: A 40 pin
pitch 2.54mm standard IDE interface on the primary controller and a Compact Flash connector
on the secondary controller.
SoundBlaster Pro hardware and Direct Sound ready AC97 Digital Audio controller.
1.4.2 DRAM
Interface
The VT82C694X supports eight banks of DRAMs up to 1.5GB. The DRAM controller supports
standard Fast Page Mode (FPM) DRAM, EDO-DRAM, Synchronous DRAM (SDRAM) and
Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous
DRAM interface allows zero wait state bursting between the DRAM and the data buffers at
66/100/133 MHz. The eight banks of DRAM can be composed of an arbitrary mixture of 1M / 2M /
4M / 8M / 16M / 32MxN DRAMs. The DRAM controller also supports optional ECC (single-bit
error correction and multi-bit detection) or EC (error checking) capability separately selectable on a
bank-by-bank basis. The DRAM controller can run at either the host CPU bus frequency (66 /100
/133MHz) or at the AGP bus frequency (66 MHz) with built-in PLL timing control.
