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NAR-5050/5070 Series User

’

s Manual

57

3.2 System Architecture

The  following  illustration  of  block  diagram  illustrated  basic  design  reference  of  PPAP-3710L-
0200,  a  highly  integrated  system  solution.  The  most  up-to-date  system  architecture  of  PPAP-
3710L-0200  includes  two  main  VLSI  chips.  It  contains  CMIC-SL  and  CSB5  to  support  mPGA
Celeron/Pentium 4 processor, DIMM, PCI bus interface, USB port, SMBus communication, and
Ultra  DMA/100  IDE  Master.  The  on-board  CSB5  chip  supports  two  UARTs,  and  hardware
monitoring.

PPAP-3710L-0200 has built-in Socket 478 to support Intel mPGA Celeron/Pentium 4 processor
(400 or 533MHz FSB) for cost-effective and high performance application.

The CMIC-SL provides a completely integrated solution for the system controller and data path
components in a Celeron/Pentium 4 processor system. It provides optimized 64-bit DDRAM
interface with one 184 pin 2.5V DIMM.

The CSB5 provides a highly integrated multifunction for the best industry applications. It
supports 2-channel dedicated Ultra ATA/33/66/100 IDE master interface, Universal Serial Bus
(

USB)

controllers and two 32-bit PCI bus interfaces.

All detailed operating relations are shown in

Fig. 3-2

(PPAP-3710L-0200 System Block

Diagram).

Figure 3-2 PPAP-3710L-0200 Block Diagram

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Summary of Contents for NAR-5050-310

Page 1: ...Communication Appliance User s Manual Revision 010 Portwell Inc 3F No 92 Sec 1 Nei Hu Rd Taipei 114 Taiwan R O C Headquarter 886 2 2799 2020 FAX 886 2 2799 1010 http www portwell com tw Email info mail portwell com tw ...

Page 2: ...d Install DIMM 5 2 6 Remove and Install DOM 5 2 7 Remove and Install Battery 6 2 8 Install HDD 7 2 9 Remove and Install PCI card 9 2 10 Remove and Install PCI card 9 2 10 Product Specifications 10 2 11 Hardware Configuration Setting 11 2 12 Install a Different Processor 14 2 13 Use a Client Computer 14 2 14 BIOS Setup Information 16 2 15 Reset to Default Information 22 2 16 WDT Information 25 2 17...

Page 3: ...l 1 2 Manual Organization This manual describes how to configure your NAR 5050 series system to meet various operating requirements It is divided into three chapters with each chapter addressing the basic concept and operation of this system Chapter 1 Introduction This section describes how this document is organized It includes brief guidelines and overview to help find necessary information Chap...

Page 4: ...herals back into the antistatic bag when they are not in use or not installed in the chassis Some circuitry on the system board can continue operating even though the power is switched off Under no circumstances should the Lithium battery cell used to power the real time clock be allowed to be shorted The battery cell may heat up under these conditions and present a burn hazard WARNING 1 CAUTION D...

Page 5: ...ntegrated in a customized 1U chassis Fig 2 1 Fig 2 2 On the front panel you will find a 4 push button LCD module EZIO three or five LAN ports and a COM port NAR 5050 310 NAR 5050 510 Fig 2 1 Front view of the chassis Fig 2 2 Rear view of the chassis 2 4 Open the Chassis ...

Page 6: ...oved from the base stand Fig 2 5 Fig 2 4 The top lead Fig 2 5 The base stand 2 5 Remove and Install DIMM Follow these steps to upgrade RAM module 1 Install the system memory by pulling the socket s arm and pressing it into the slot gently Fig 2 6 2 7 Fig 2 6 Eject a DIMM module Fig 2 7 Install DIMM 2 6 Remove and Install Compact Flash Card 1 Insert the Compact Flash Card Fig 2 8 into the CF interf...

Page 7: ...n of Compact Flash Card is shown as Fig 2 10 Fig 2 10 Completion of Compact Flash Card connection 2 7 Remove and Install Battery 1 Press the metal clip back to eject the button battery Fig 2 11 2 Replace it with a new one by pressing the battery with fingertip to restore the battery Fig 2 12 Fig 2 11 Eject the battery Fig 2 12 Restore the battery ...

Page 8: ...to install the HDD 1 Fasten the four screws to lock HDD and bracket together Fig 2 13a 2 13b Fig 2 13a A 2 5 HDD and the HDD bracket Fig 2 13b Fix HDD to the bracket 2 Connect the IDE cable to HDD Fig 2 14 3 Connect IDE cable to PPAP 3710L 0200 Fig 2 15 Fig 2 14 Connect IDE cable to HDD Fig 2 15 Connect IDE cable to PPAP 3710L 0200 4 Fix all four screws back Fig 2 16 Fig 2 16 Drive all four screws...

Page 9: ... the top lead Fig 2 17 2 Remove the screw on the side Fig 2 18 Fig 2 17 The top lead Fig 2 18 Remove the screw on the side 3 Push the PCI add on card into the PCI slot Fig 2 19 Fig 2 19 Push the PCI add on card into the PCI slot Fig 2 20 Fasten the screw into the side 4 Fasten the screw from the side Fig 2 20 5 Drive the screws on the top lead Fig 2 21 Fig 2 21 Drive the screws back to lock the to...

Page 10: ...screws on the top lead and remove the top lead Fig 2 22 7 Push the PCI X add on card into the PCI X slot Fig 2 23 Fig 2 22 The top lead Fig 2 23 Push the PCI X add on card into the PCI X slot 8 Fasten the screw from the side Fig 2 24 9 Drive the screws back to lock the top lead Fig 2 25 Fig 2 24 Fasten the screw into the side Fig 2 25 Drive the screws back to lock the top lead ...

Page 11: ...high speed I O peripheral devices Auxiliary I O Interfaces System reset switch power okay LED and HDD LED interface Power Input Support one AC input jack power requirement 110V 220V PCI Slot One PCI slot for add on PCI card PCI X Slot One PCI X slot for add on PCI X card On board Ethernet One Intel 82551 10 100 Fast Ethernet controllers with RJ 45 interface for NAR 5050 310 and NAR 5050 510 One In...

Page 12: ...or certain features Some of the jumpers are configurable for system enhancement The others are for testing purpose only and should not be altered To select any option cover the jumper cap over Short or remove NC it from the jumper pins according to the following instructions Here NC stands for Not Connected Jumper Table Jumper Function Default Setting JP1 1 2 Reset to Default function NC Normal JP...

Page 13: ...NAR 5050 5070 Series User s Manual 12 Figure 2 22 PPAP 3710L 0200 Jumper Table ...

Page 14: ...J5 POWER GREEN IDE ORANGE LED J6 USB J7 CPU FAN J8 SYSTEM FAN 1 J9 SYSTEM FAN 2 J10 SYSTEM FAN 3 J11 SYSTEM FAN 4 J12 FORNT PANEL FAN J13 PS2 KEYBOARD MOUSE J14 COM2 J15 COM1 J16 PCI32 J17 PCI X J18 DIMM 1 J19 DIMM 2 J20 LAN 2 J22 LAN 3 J24 IDE CNANNEL0 44pin J25 IDE CHANNEL1 CF CARD J26 CHASSIS INTRUSION J31 POWER ON J34 IDE CNANNEL0 40pin ...

Page 15: ... jumper settings properly for all boards Remove CPU 1 Unlock the cooling fan first 2 Lift the lever of CPU socket outwards and upwards to the other end 3 Carefully lift up the existing CPU to remove it from the socket 4 Follow the steps of CPU installation to change to another one or place handling bar to close the opened socket Configure Processor Speed The system was designed to self detect its ...

Page 16: ...nter a name to create new dial 3 For the connection settings make it Direct to Com1 4 Please make the port settings to Baud rate 19200 Parity None Data bits 8 Stop bits 1 5 Turn on the power of NAR 5050 series after following screen was shown ...

Page 17: ... with the Award BIOS within Flash ROM The BIOS has a built in setup program that allows users to modify the basic system configuration easily This type of information is stored in CMOS RAM so that it still retains during power off periods When system is turned on NAR 5050 series communicates with peripheral devices and checks its hardware resources against the configuration information stored in t...

Page 18: ...navigate within Setup menu Key Function Up Move to the previous item Down Move to the next item Left Move to the item on the left menu bar Right Move to the item on the right menu bar Enter Enter the item you desired PgUp Increase the numeric value or make changes PgDn Decrease the numeric value or make changes Increase the numeric value or make changes Decrease the numeric value or make changes E...

Page 19: ...keys to highlight the item and then use the PgUp PgDn or keys to select the value or number you want in each item and press Enter to certify it Follow command keys in CMOS Setup table to change Date Time Drive type and Boot Sector Virus Protection Status Screen Shot Phoenix Award BIOS CMOS Setup Utility Standard CMOS Setup Utility Date Wed Jan 17 2001 Time 16 51 13 IDE Primary Master None IDE Prim...

Page 20: ...d operation shadowing and security Screen Shot Phoenix Award BIOS CMOS Setup Utility Advanced BIOS Features Console Redirection Disabled Agent connect via NULL Agent wait time min 1 Agent after boot Disabled Boot Seq Floppy Setup Press Enter Console Redirection Press Enter Cache Setup Press Enter Virus Warning Disable Hyper Threading Technology Enabled Quick Power On Self Test Enabled Boot Up NumL...

Page 21: ... warning feature for IDE Hard Disk boot sector protection Enabled Enable VIRUS warning Disabled Disabled VIRUS warning Hyper Threading Technology For WindowsXP and Linux 2 4 x OS optimized for Hyper Threading Technology Enabled Enable Hyper Threading Technology Disabled Disabled Hyper Threading Technology Quick Power On Self Test This category speeds up Power On Self Test POST after you power up t...

Page 22: ...tic Delay Msec Set the delay time after the key is held down before it begins to repeat the keystroke The choice 250 500 750 and 1000 Security Option Select whether the password is required every time the system boots or only when entering setup System The system will not boot and access to Setup will be denied if the correct password is not entered at the prompt Setup The system will boot and acc...

Page 23: ... due to RST2DFT flag is 0 RST2DFT flag can be polled and read its status periodically This flag can be set to 1 by reading the SET_RST2DFT I O port and back to the normal state SET_RST2DFT I O port Address is CDEFh by BIOS initiation and can be changed by changing two another I O port content I O Port 0F57h contains SET_RST2DFT I O port Address A15 A8 I O Port 0F56h contains SET_RST2DFT I O port A...

Page 24: ...FG3_Bit1P0 RD_R2D Step 2 Enable GPIO function Set GPIO_Index 30h_Bit0 mov dx Index_IO_Port Point to GPIO_LDN LDN 7 mov al 07 out dx al mov dx Data_IO_Port mov al GPIO_LDN out dx al mov dx Index_IO_Port Read Index 30h First mov al 30h out dx al mov dx Data_IO_Port in al dx or al 01h Set Bit0 to 1 mov ah al keep in AH mov dx Index_IO_Port mov al 30h out dx al mov dx Data_IO_Port mov al ah out dx al ...

Page 25: ... 60h out dx al mov dx Data_IO_Port in al dx mov bh al High Byte I O Base Addr BH mov dx Index_IO_Port mov al 61h Read Index 61h out dx al mov dx Data_IO_Port in al dx mov bl al High Byte I O Base Addr BL mov dx bx Load Base Addr to DX RD_R2D Step 6 Read GPID4_bit5 GPIO45 Status Offset_0B is the Addr of GPDI4 R O GPDI4_Bit5 is for GPIO45 xor bx bx mov bl GPDI4 add dx bx Point to GPDI offset in al d...

Page 26: ...PU boards that implement NS PC87417 Super I O WDT onboard Pin55 of NS PC87417 is defined as WDT output pin that will issue an Active low pulse 250ms pulse when it expires without any S W refresh The following three procedures are the assembly codes to enable refresh and disable WDT Any application can use WDT to monitor S W process Enable WDT to start monitoring S W process Refresh WDT before WDT ...

Page 27: ... dx or al 80h Set Bit7 to 1 mov ah al keep in AH mov dx Index_IO_Port mov al SIOCFG2 out dx al mov dx Data_IO_Port mov al ah out dx al SIOCFG2_Bit7P1 Enable WDT Step 2 Enable SWC function Set SWC_Index 30h_Bit0 mov dx Index_IO_Port Point to SWC_LDN LDN 4 mov al 07 out dx al mov dx Data_IO_Port mov al SWC_LDN out dx al mov dx Index_IO_Port Read Index 30h First mov al 30h out dx al mov dx Data_IO_Po...

Page 28: ...set 0fh_Bit 1 0 P 1 1 add dx 0fh Point to I O Base Addr 0fh in al dx Read this I O port value first or al 03 Select Bank 3 of SWC out dx al sub dx 0fh dx back to I O base Addr Enable WDT Step 5 Program WDTO Twd Offset 11h Write Twd before enabling all WDT enable bits xor bx bx mov bl WDTO add dx bx Point to WDTO offset mov al ch Write the Twd value in minutes out dx al sub dx bx dx back to I O bas...

Page 29: ...se Addr Enable WDT Step 8 Enable SW_WD_TRG Offset 10h_Bit7P1 Reload Twd and start count down xor bx bx mov bl WDCTL add dx bx Point to WDCTL offset in al dx Read this I O port value first or al 80h WDCTL_bit7P1 Set SW_WD_TRG out dx al sub dx bx dx back to I O base Addr pop bx pop cx pop ax pop dx ret WDT enable ENDP Refresh WDT Index_IO_Port dw 002Eh Data_IO_Port dw 002Fh SWC_LDN db 04h SIOCFG2 db...

Page 30: ...rt mov al ah out dx al SIOCFG2_Bit7P1 Refresh WDT Step 2 Enable SWC function Set SWC_Index 30h_Bit0 mov dx Index_IO_Port Point to SWC_LDN LDN 4 mov al 07 out dx al mov dx Data_IO_Port mov al SWC_LDN out dx al mov dx Index_IO_Port Read Index 30h First mov al 30h out dx al mov dx Data_IO_Port in al dx or al 01h Set Bit0 to 1 mov ah al keep in AH mov dx Index_IO_Port mov al 30h out dx al mov dx Data_...

Page 31: ...ork properly in case the Twd needs to be changed whenever Refreshing WDT Refresh WDT Step 5 Disable SW_WD_TREN Offset 12h_Bit7P0 Not allow S W to trigger WDT xor bx bx mov bl WDCFG add dx bx Point to WDCFG offset in al dx Read this I O port value first and al 7Fh WDCFG_bit7P0 Disable SW_WD_TREN out dx al sub dx bx dx back to I O base Addr Refresh WDT Step 6 Disable SW_WD_TRG Offset 10h_Bit7P0 Inac...

Page 32: ... Refresh WDT Step 9 Enable SW_WD_TREN Offset 12h_Bit7P1 Allow S W to trigger WDT xor bx bx mov bl WDCFG add dx bx Point to WDCFG offset in al dx Read this I O port value first or al 80h WDCFG_bit7P1 Set SW_WD_TREN out dx al sub dx bx dx back to I O base Addr Refresh WDT Step 10 Enable SW_WD_TRG Offset 10h_Bit7P1 Reload Twd and start count down xor bx bx mov bl WDCTL add dx bx Point to WDCTL offset...

Page 33: ... in al dx or al 80h Set Bit7 to 1 mov ah al keep in AH mov dx Index_IO_Port mov al SIOCFG2 out dx al mov dx Data_IO_Port mov al ah out dx al SIOCFG2_Bit7P1 Disable WDT Step 2 Enable SWC function Set SWC_Index 30h_Bit0 mov dx Index_IO_Port Point to SWC_LDN LDN 4 mov al 07 out dx al mov dx Data_IO_Port mov al SWC_LDN out dx al mov dx Index_IO_Port Read Index 30h First mov al 30h out dx al mov dx Dat...

Page 34: ... dx 0fh Point to I O Base Addr 0fh in al dx Read this I O port value first or al 03 Select Bank 3 of SWC out dx al sub dx 0fh dx back to I O base Addr Disable WDT Step 5 Disable SW_WD_TREN Offset 12h_Bit7P0 Not allow S W to trigger WDT xor bx bx mov bl WDCFG add dx bx Point to WDCFG offset in al dx Read this I O port value first and al 7Fh WDCFG_bit7P0 Disable SW_WD_TREN out dx al sub dx bx dx bac...

Page 35: ...IO_Port NS PC87417 Data I O Port 2Fh GPIO_LDN System Wake Up Control Logical Device Number 07 GPSEL Index 0F0h from GPIO LDN Set Port Bit 6 4 and Pin Bit2 0 GPCFG1 Index 0F1h from GPIO LDN Set GPIO direction type GPDO3 Offset from I O base Addr for GPIO 08h GPDI3 Offset from I O base Addr for GPIO 09h Input None Stack present output CH bit 7 GPO30 JP1 on PPAP LED2 test module 6 GPO37 JP2 on PPAP L...

Page 36: ...n al dx or al 01h Set Bit0 to 1 mov ah al keep in AH mov dx Index_IO_Port mov al 30h out dx al mov dx Data_IO_Port mov al ah out dx al Index30h_bit0P1 Get_GPI Step 2 Read GPIO I O Base Address Index 60h contains A15 A8 Index 61h contains A7 A0 mov dx Index_IO_Port Read Index 60h mov al 60h out dx al mov dx Data_IO_Port in al dx mov bh al High Byte I O Base Addr BH mov dx Index_IO_Port mov al 61h R...

Page 37: ...ap EBX high and low word mov bl 00h EBX_Bit 23 16 mov bh GPDI3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY call get GPDI jc set_bit7 if carry then Bit7 1 and ch 7fh else Bit7 0 jmp next_bit6 set_bit7 or Ch 80h next_bit6 Bit7 of Ch end Bit6 of Ch start GPIO37 JP2 of test module EBX_Bit 31 24 GPDI3 09h EBX_Bit 23 16 MASK bit which bit GPIO37 07h EBX_Bi...

Page 38: ... GPIO31 01h EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value or 06h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 31h Call LOOP_GET_GPI_CARRY get the bit to CARRY flag mov bl 31h EBX_Bit 7 0 31h mov dx Index_IO_Port Read Index F1h first mov al GPCFG1 out dx al mov dx Data_IO_Port in al dx or al 06h OR 06h mov bh al EBX_Bit 15 8 ror ebx 10h Swap EBX high and low word mov bl 01h EBX_Bit 23 ...

Page 39: ... low word mov bl 06h EBX_Bit 23 16 mov bh GPDI3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY call get GPDI jc set_bit4 if carry then Bit4 1 and ch 0EFh else Bit4 0 jmp next_bit3 set_bit4 or Ch 10h next_bit3 Bit4 of Ch end Bit3 of Ch start GPIO32 JP5 of test module EBX_Bit 31 24 GPDI3 09h EBX_Bit 23 16 MASK bit which bit GPIO32 02h EBX_Bit 15 8 GPCFG1 ...

Page 40: ... GPIO35 05h EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value or 06h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 35h Call LOOP_GET_GPI_CARRY get the bit to CARRY flag mov bl 35h EBX_Bit 7 0 35h mov dx Index_IO_Port Read Index F1h first mov al GPCFG1 out dx al mov dx Data_IO_Port in al dx or al 06h OR 06h mov bh al EBX_Bit 15 8 ror ebx 10h Swap EBX high and low word mov bl 05h EBX_Bit 23 ...

Page 41: ...EBX high and low word mov bl 03h EBX_Bit 23 16 mov bh GPDI3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GET_GPI_CARRY call get GPDI jc set_bit1 if carry then Bit1 1 and ch 0FDh else Bit1 0 jmp next_bit0 set_bit1 or Ch 02h next_bit0 Bit1 of Ch end Bit0 of Ch start GPIO34 JP8 of test module EBX_Bit 31 24 GPDI3 09h EBX_Bit 23 16 MASK bit which bit GPIO34 04h EBX_Bit ...

Page 42: ...set_bit0 or Ch 01h all_8bits_read 8 GPI bits read and kept in CH and CH will be returned Bit0 of Ch end pop ax pop ebx pop edx ret GET_GPI_STATUS_CH ENDP LOOP_GET_GPI_CARRY GET the GPI pin status and returned to Carry Flag INPUT EBX_Bit 31 24 GPDI Offset value EBX_Bit 23 16 MASK bit which bit EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin STACK PRESENT...

Page 43: ...dd dx ax Point to Offset Addr in al dx Get GPDI push ax save al to stack mov al bh DX Back to I O Base Addr sub dx ax rol edx 10h Restore GPIO I O Base Addr to EDX_Bit 31 16 pop ax restore al from stack xor bh bh bh 0 for bit test need BX bt ax bx MASK bit relates to the GPI pin status copy the bit to carry flag and return ret Return LOOP_GET_GPI_CARRY ENDP GPO_OUT_BYTE_DH GPO_OUT_BYTE_DH Output G...

Page 44: ...ush edx push ebx push ax push cx mov ch dh Save dh Twd value in ch GPO_OUT Step 1 Enable GPIO function Set GPIO_Index 30h_Bit0 mov dx Index_IO_Port Point to GPIO_LDN LDN 7 mov al 07 out dx al mov dx Data_IO_Port mov al GPIO_LDN out dx al mov dx Index_IO_Port Read Index 30h First mov al 30h out dx al mov dx Data_IO_Port in al dx or al 01h Set Bit0 to 1 mov ah al keep in AH mov dx Index_IO_Port mov ...

Page 45: ...ue or 07h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 30h mov bl 30h EBX_Bit 7 0 30h mov dx Index_IO_Port Read Index F1h first mov al GPCFG1 out dx al mov dx Data_IO_Port in al dx or al 07h OR 07h mov bh al EBX_Bit 15 8 ror ebx 10h Swap EBX high and low word mov bl ch and bl 80h Other bits 0 except Bit7 ror bl 07h Bit7 rotate to Bit0 for EBX_Bit 23 16 mov bh GPDO3 EBX_Bit 31 24 rol ebx 10h...

Page 46: ... ror bl 07h Bit7 rotate to Bit0 for EBX_Bit 23 16 Keep bit7 end add bl bh Bit7 and Bit6 of Ch programmed mov bh GPDO3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GPO_BITS call output GPDO Bit6 of Ch end Bit5 of Ch start GPIO31 EBX_Bit 31 24 GPDO Offset value 08h EBX_Bit 23 16 GPO Data Bit5 of Ch Bit1 other bits 0 EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value...

Page 47: ...igh and low word call LOOP_GPO_BITS call output GPDO Bit5 of Ch end Bit4 of Ch start GPIO36 EBX_Bit 31 24 GPDO Offset value 08h EBX_Bit 23 16 GPO Data Bit4 of Ch Bit6 other bits 0 EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value or 07h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 36h mov bl 36h EBX_Bit 7 0 36h mov dx Index_IO_Port Read Index F1h first mov al GPCFG1 out dx al mov dx Data_...

Page 48: ...nd Bit3 of Ch start GPIO32 EBX_Bit 31 24 GPDO Offset value 08h EBX_Bit 23 16 GPO Data Bit3 of Ch Bit2 other bits 0 EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value or 07h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 32h mov bl 32h EBX_Bit 7 0 32h mov dx Index_IO_Port Read Index F1h first mov al GPCFG1 out dx al mov dx Data_IO_Port in al dx or al 07h OR 07h mov bh al EBX_Bit 15 8 ror ebx ...

Page 49: ... GPDO3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GPO_BITS call output GPDO Bit3 of Ch end Bit2 of Ch start GPIO35 EBX_Bit 31 24 GPDO Offset value 08h EBX_Bit 23 16 GPO Data Bit2 of Ch Bit5 other bits 0 EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data read value or 07h EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin 35h mov bl 35h EBX_Bit 7 0 35h mov dx Index_IO_Port...

Page 50: ...be saved since Programmed and bl 80h Other bits 0 except Bit7 ror bl 07h Bit7 rotate to Bit0 for EBX_Bit 23 16 Keep bit7 6 5 4 3 end add bl bh Bit7 Bit6 Bit5 Bit4 Bit3 and Bit2 of Ch programmed mov bh GPDO3 EBX_Bit 31 24 rol ebx 10h Restore the Swap of EBX high and low word call LOOP_GPO_BITS call output GPDO Bit2 of Ch end Bit1 of Ch start GPIO33 EBX_Bit 31 24 GPDO Offset value 08h EBX_Bit 23 16 ...

Page 51: ...xcept Bit5 ror bl 04h Bit5 rotate to Bit1 for EBX_Bit 23 16 add bh bl Add BIt5 of ch in BH mov bl ch and bl 40h Other bits 0 except Bit6 rol bl 01h Bit6 rotate to Bit7 for EBX_Bit 23 16 add bh bl Add BIt6 of ch in BH mov bl ch Bit7 of Ch needs to be saved since Programmed and bl 80h Other bits 0 except Bit7 ror bl 07h Bit7 rotate to Bit0 for EBX_Bit 23 16 Keep bit7 6 5 4 3 2 end add bl bh Bit7 Bit...

Page 52: ...3h Bit2 rotate to Bit5 for EBX_Bit 23 16 add bh bl Add Bit2 of ch in BH mov bl ch and bl 08h Other bits 0 except Bit3 ror bl 01h Bit3 rotate to Bit2 for EBX_Bit 23 16 add bh bl Add Bit3 of ch in BH mov bl ch and bl 10h Other bits 0 except Bit4 rol bl 02h Bit4 rotate to Bit6 for EBX_Bit 23 16 add bh bl Add Bit4 of ch in BH mov bl ch and bl 20h Other bits 0 except Bit5 ror bl 04h Bit5 rotate to Bit1...

Page 53: ... 24 GPDO Offset value EBX_Bit 23 16 GPO Data EBX_Bit 15 8 GPCFG1 LDN07_Index_F1h Data EBX_Bit 7 0 GPSEL LDN07_Index_F0h Data Port and Pin EDX_Bit 31 16 GPIO I O Base Address STACK PRESENT OUTPUT None Modified Register DX AX LOOP_GPO_BITS PROC NEAR mov dx Index_IO_Port Program GPSEL first port and Pin mov al GPSEL out dx al mov dx Data_IO_Port mov al bl out dx al mov dx Index_IO_Port Program GPCFG1...

Page 54: ...IO I O Base Addr to EDX_Bit 31 16 ret Return LOOP_GPO_BITS ENDP FIXED_DELAY Input CX count of 15 microseconds to wait STACK PRESENT Output NONE Register destroyed CX This routine is called to wait for 15 microseconds count in CX then return Gives a programmed software delay FIXDELAY PROC NEAR push dx push ax pushf mov dx 61h in al dx jmp 2 jmp 2 and al 00010000b mov ah al fixed_delay_1 in al dx jm...

Page 55: ...t push cx loop_message mov cx 03h loop_message_init cmp cx 03h jne loop_message1 mov ah 02h mov dl 2fh cx 3 display int 21h dec cx lea dx promp_bs back space ASCII 08 mov ah 9 int 21h push cx mov cx 0010h call fixdelay pop cx jmp loop_message_init loop_message1 cmp cx 02h jne loop_message2 mov ah 02h mov dl 7Ch cx 2 display int 21h dec cx lea dx promp_bs back space ASCII 08 mov ah 9 int 21h push c...

Page 56: ...ck space ASCII 08h mov ah 9 int 21h push cx mov cx 0010h call fixdelay pop cx jmp loop_message_init loop_message3 mov ah 02h mov dl 2Dh cx 1 display int 21h lea dx promp_bs back space ASCII 08h mov ah 9 int 21h push cx mov cx 0010h call fixdelay pop cx pop cx total_count dec cx jz proc_return Return jmp total_count proc_return pop dx pop cx pop ax ret LOOP_DISPLAY_4_CHAR ENDP END programstart ...

Page 57: ...ard is utilized with Intel mPGA Celeron and Intel mPGA Pentium 4 processors and 184 pin DIMM up to 4 GB DRAM The enhanced on board PCI IDE interface supports 2 drives up to PIO mode 4 timing and Ultra DMA 100 synchronous mode feature The on board Server Works CSB5 chipset integrates two serial ports driven by two high performance 16C550 compatible UARTs to provide 16 byte send receive FIFOs In add...

Page 58: ...as built in Socket 478 to support Intel mPGA Celeron Pentium 4 processor 400 or 533MHz FSB for cost effective and high performance application The CMIC SL provides a completely integrated solution for the system controller and data path components in a Celeron Pentium 4 processor system It provides optimized 64 bit DDRAM interface with one 184 pin 2 5V DIMM The CSB5 provides a highly integrated mu...

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