NAR-5050/5070 Series User
’
s Manual
24
mov al,45h
out dx,al
;
RD_R2D Step 4 :Define GPIO45 as an input pin with internal Pull high
;( GPCFG1_P46h )
mov dx,Index_IO_Port
mov al,GPCFG1
out dx,al
mov dx,Data_IO_Port
mov al,46h
out dx,al
;
RD_R2D Step 5 : Read GPIO I/O Base Address
;( Index-60h contains A15---A8, Index-61h contains A7---A0 )
mov dx,Index_IO_Port
; Read Index 60h
mov al,60h
out dx,al
mov dx,Data_IO_Port
in al,dx
mov bh,al
; High Byte I/O Base Addr --> BH
mov dx,Index_IO_Port
mov al,61h
; Read Index 61h
out dx,al
mov dx,Data_IO_Port
in al,dx
mov bl,al
; High Byte I/O Base Addr --> BL
mov dx,bx
; Load Base Addr to DX
;
RD_R2D Step 6 : Read GPID4_bit5 ( GPIO45 ) Status
;Offset_0B is the Addr. of GPDI4 ( R/O ), GPDI4_Bit5 is for GPIO45
xor bx,bx
mov bl,GPDI4
add dx,bx
; Point to GPDI offset
in al,dx
; Read GPIO45 Status ( Bit 5 of AL )
sub dx,bx
; dx back to I/O base Addr.
bt ax,05h
; Bit 5 copy to Carry Flag and return.
pop ax
pop bx
pop dx
ret
RST2DFT_Flag_Read ENDP
