PLX PCI-Proto Lab/PLX-S, Technical Manual

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The following information is supposed to help avoid errors and make work with
PCI-Proto LAB/PLX-S easier. We will list them here without putting them any specific or-
der.
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PCI-Proto LAB/PLX-S is initialized in such a fashion that there are four I/O and memory
address regions. They make the following accesses possible:
PCI region 0 mem mapped, used for host access to Local /Runtime /DMA registers
PCI region 1 I/O mapped, used for host access to Local /Runtime /DMA registers
PCI region 2 I/O mapped, address range 16 bytes, corresponds with local
address space 0
PCI region 3 mem mapped, address range 16 bytes, corresponds with local
address space 1
PCI region 4 disabled, corresponds with local address space 2, not used in
prototype boards delivered state
PCI region 5 disabled, corresponds with local address space 3, not used in
prototype boards delivered state
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The bus range of both local spaces (0 and 1) is initialized to 32 bit. It is possible to access
the latches installed as an example application with 32 bit, 16 bit and 8 bit read -or write
commands. You can access to the latches with I/O (use base address of PCI -Region 2) or
memory based commands (use base address of PCI region 3).
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If you read and write 32 bit data you can use the address offset 0 only, if you read and
write 16 bit data you can use the address offset 0 or 2 and if you read and write 8 bit data
you might use the address offsets 0, 1, 2 or 3.
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PCI-Proto LAB/PLX-S has its own Vendor ID, Device ID, Sub vendor ID and Sub sys-
tem ID. The Vendor ID (10B5h) and Device ID (9030h) is given by the PCI-SIG to PLX
Technology and should not be changed. The Sub device ID (9030h) was issued from PLX
Technology for the used type of PCI controller and should not be changed too. The Sub
system ID (2263h) was issued specifically for the product
PCI-Proto LAB/PLX-S
. The
user may apply for his own Sub system ID from PLX Technology for his application. Ask
your local PLX dealer for this reason.