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13 

 

6.4.  Connection Tables 

 

Connection Table Pin Header JP3, JP5 

 

 

Pin 

Name 

Pin 

Name 

01 

+3,3V 

02 

+5V 

03 

out_data 00 

04 

out_data 01 

05 

out_data 02 

06 

out_data 03 

07 

out_data 04 

08 

out_data 05 

09 

out_data 06 

10 

out_data 07 

11 

GND 

12 

GND 

13 

out_data 08 

14 

out_data 09 

15 

out_data 10 

16 

out_data 11 

17 

out_data 12 

18 

out_data 13 

19 

out_data 14 

20 

out_data 15 

21 

+3,3V 

22 

+5V 

 
 

Connection Table Pin Header JP3 (User bus/ data output 0 - 15) 

 

 
 
 
 

Pin 

Name 

Pin 

Name 

01 

+5V 

02 

+3,3V 

03 

out_data 31 

04 

out_data 30 

05 

out_data 29 

06 

out_data 28 

07 

out_data 27 

08 

out_data 26 

09 

out_data 25 

10 

out_data 24 

11 

GND 

12 

GND 

13 

out_data 23 

14 

out_data 22 

15 

out_data 21 

16 

out_data 20 

17 

out_data 19 

18 

out_data 18 

19 

out_data 17 

20 

out_data 16 

21 

+5V 

22 

+3,3V 

 
 

Connection Table Pin Header JP5 (User bus/ data output 16 - 31) 

 

Summary of Contents for PCI-Proto Lab/PLX-S

Page 1: ...PCI Proto Lab PLX S Technical Manual HK Me systeme GmbH K penicker Str 325 12555 Berlin Germany November 2007...

Page 2: ...___________________ 9 6 2 Electronic Circuit __________________________________________________ 10 6 3 Connection Diagrams _______________________________________________ 11 6 4 Connection Tables_____...

Page 3: ...t the marked place PCI Proto LAB PLX S is designed as a universal board that supports either 3 3V or 5V PCI bus operation It s operating voltage for all electronic circuits is 3 3V PCI Proto LAB PLX S...

Page 4: ...ace supports up to 32bits of local data and up to 28bits of latched local addresses User specific systems control the data exchange effectively through the local bus interface with the aid of classica...

Page 5: ...S is equipped with latches for intermediate storage of 32bit data input or output The additionally required logic is placed in a EPLD device which also reserves space for user specific modifications I...

Page 6: ...nge of both local spaces 0 and 1 is initialized to 32 bit It is possible to access the latches installed as an example application with 32 bit 16 bit and 8 bit read or write commands You can access to...

Page 7: ...ere are two different variations to get access to the data latches I O commands use PCI address region 2 corresponds with local address space 0 or Memory commands use PCI address region 3 corresponds...

Page 8: ...8 6 Appendix...

Page 9: ...9 6 1 Block Diagram...

Page 10: ...10 6 2 Electronic Circuit In this shortened manual version this chapter is not included...

Page 11: ...11 6 3 Connection Diagrams Connection Diagram Component Side...

Page 12: ...12 Connection Diagram Solder Side...

Page 13: ...out_data 12 18 out_data 13 19 out_data 14 20 out_data 15 21 3 3V 22 5V Connection Table Pin Header JP3 User bus data output 0 15 Pin Name Pin Name 01 5V 02 3 3V 03 out_data 31 04 out_data 30 05 out_d...

Page 14: ...ta 29 18 in_data 28 19 in_data 31 20 in_data 30 21 5V 22 3 3V Connection Table Pin Header JP6 User bus data input 16 31 Pin Name Pin Name 01 3 3V 02 5V 03 in_data 14 04 in_data 15 05 in_data 12 06 in_...

Page 15: ...l bus data 0 15 Pin Name Pin Name 01 5V 02 3 3V 03 LD 16 04 LD 17 05 LD 18 06 LD 19 07 LD 20 08 LD 21 09 LD 22 10 LD 23 11 GND 12 GND 13 LD 24 14 LD 25 15 LD 26 16 LD 27 17 LD 28 18 LD 29 19 LD 30 20...

Page 16: ...tput 30 GP1 LLK input output 31 GP0 WT input output 32 GND power supply Connection Table Pin Header JP20 Local bus addresses 0 31 Pin Name PCI9030 Functions Pin Name PCI9030 Functions 01 LPMESET input...

Page 17: ...in Supply active 1 3 3V Main Supply active 1 16 open 5V Main Supply active 1 3 3V Main Supply active 1 17 open 5V Main Supply active 1 3 3V Main Supply active 1 18 open 5V Main Supply active 1 3 3V Ma...

Page 18: ...O20 7 LA2 input 29 not used I O21 8 ADS input 30 LBE3 input 9 LA3 input 31 LBE2 input 10 TDI ISP Interface 32 TDS ISP Interface 11 GP1 LLK in output inactive 33 LCLK CLK1 I1 12 GND power supply 34 GND...

Page 19: ...19 6 7 Component Diagram...

Page 20: ...20 6 8 Oscillograms...

Page 21: ...21 6 8 1 Oscillogram host accesses to the example application at the local bus local ready controlled...

Page 22: ...22 6 8 2 Oscillogram 32bit host write access to the local bus PlxMon command ol adr 0h local ready controlled...

Page 23: ...23 6 8 3 Oscillogram 32bit host read access from the local bus PlxMon command il adr local ready controlled...

Page 24: ...24 6 8 4 Oscillogram 32bit host write accesss to the local bus PlxMon command ol adr FFFFh local ready controlled...

Page 25: ...25 6 8 5 Oscillogram 32bit host read access from the local bus with view to a data line LDx PlxMon command il adr local ready controlled...

Page 26: ...26 6 9 Source Code EPLD M4A3 64 32 6 9 1 ABEL based Source Code 6 9 2 VHDL based Source Code In this shortened manual version this chapter is not included...

Page 27: ...chter Fax 81 428 77 7010 Email RDSCONSLT aol com Contact Person Takao Fujii Email sales dsp tdi com Taiwan Spain Bentech Computer Systems Corp Gerhard Kassner 7F 3 No 23 Lane 169 Kang Ning Str Servici...

Page 28: ...eb Addresses http www plxtech com http www latticesemi com http www pcisig com http www pci tools com http www pci tools de 6 12 Technical Product Features Features Bus interface PCI in compliance to...

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