PLX Technology PEX 8505, Hardware Reference Manual

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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TESTMODE2
TESTMODE3
TESTMODE0
TESTMODE1
UP_PORT0
UP_PORT1
UP_PORT2
PORTCFG1
PORTCFG0
PROCMON
JTAG_TDO_0
VDD33A
JTAG_TDO
UP_PORT0
UP_PORT1
UP_PORT2
PORTCFG0
PORTCFG1
DIODE_N
DIODE_P
JTAG_TCK
JTAG_TRSTN
JTAG_TDI
JTAG_TMS
EECSN
EEDI
EESK
EEDO
EECSN_0
EESK_0
EEDO_0
I2C_ADDR0
I2C_ADDR1
I2C_ADDR2
FATAL_ERRN
PLLBYPASSN
FASTBRGN
PROBEN
SERDESMODEN
DEBUGSEL1
DEBUGSEL0
I2C_SCL
I2C_SDA
SPARE0
SPARE1
SPARE2
EEDI_0
EEDO0
PEX_INTAN
VDD_3.3V
VDD_VTT VDD_1.0V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_VTT VDD_3.3V VDD_1.0V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_VTT VDD_3.3V VDD_1.0V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
REFCLKP0 {8}
REFCLKN0 {8}
PERSTN {5,6,7,8,9}
Title
Size Document Number Rev
Date: Sheet of
91-0076-001-A 001
PEX8505RDK - PEX8505 Power, Misc.
PLX Technology, Inc.
870 Maude Avenue
Sunnyvale, CA 94085
www.plxtech.com
C
4 9 Monday, October 01, 2007
Title
Size Document Number Rev
Date: Sheet of
91-0076-001-A 001
PEX8505RDK - PEX8505 Power, Misc.
PLX Technology, Inc.
870 Maude Avenue
Sunnyvale, CA 94085
www.plxtech.com
C
4 9 Monday, October 01, 2007
Title
Size Document Number Rev
Date: Sheet of
91-0076-001-A 001
PEX8505RDK - PEX8505 Power, Misc.
PLX Technology, Inc.
870 Maude Avenue
Sunnyvale, CA 94085
www.plxtech.com
C
4 9 Monday, October 01, 2007
VOLTAGE MEASUREMENT POINTS
CLEARLY LABEL, AND PLACE CLOSE TO U1.
I2C HEADERS
TPV38-40 AND GV16-18 SHOULD
BE PLACED CLOSE TO U1.
FINISHED HOLE SIZE SHOULD BE
34-MIL
GV12-15 SHOULD BE 60-MIL PAD/34-MIL
FINISHED HOLE. PROVIDE SILKSCREEN
LABELS FOR THESE VIAS.
TPV30 - TPV31 SHOULD HAVE A 20-MIL
FINISHED HOLE.TPV28-TPV29 SHOULD HAVE A
30-MIL FINISHED HOLE.
GROUND POST HOLES
TPV32 - TPV37 SHOULD
HAVE A 20-MIL FINISHED
HOLE.
STRAP_PORTCFG[1:0]
00b
01b
10b
x1
x2
PEX 8505 PORT CONFIGURATION
Port 0 Port 1 Port 2 Port 3 Port 4
x2
x1 x1 x1 x1
x1 x1
Port 5
x1 x1 x1 x1 x2
NOTE: RDK hardwired setting is 00b.
STRAP_UPSTREAM_PORT_SEL[2:0]
000b Port 0
Port 1
Port 2
Port 3
Port 4
001b
010b
011b
100b
NOTE: RDK default setting is 000b.
R23 NL, 0 R23 NL, 0
C45
0.1uF
C45
0.1uF
GV14 GV14
C41
0.022uF
C41
0.022uF
C24
1uF
C24
1uF
TPV36 TPV36
R30 NL, 0 R30 NL, 0
1 2
JP5
HDR, 1X2
JP5
HDR, 1X2
GV18 GV18
C28
0.1uF
C28
0.1uF
C22
10uF
C22
10uF
C23
10uF
C23
10uF
TPV35 TPV35
R19 5.1K R19 5.1K
GV15 GV15
C38
0.01uF
C38
0.01uF
C31
0.1uF
C31
0.1uF
R29 0 R29 0
TPV33 TPV33
C48
0.1uF
C48
0.1uF
TPV32 TPV32
1
2
3
4 5
6
7
8
RN4
5.1K
RN4
5.1K
R28 0 R28 0
R36 2.26K 1% R36 2.26K 1%
R22 NL, 0 R22 NL, 0
C29
0.1uF
C29
0.1uF
1
2
3
4 5
6
7
8
RN3
5.1K
RN3
5.1K
1
2 4
3
ON
SW3
NL, SW SMT-2
ON
SW3
NL, SW SMT-2
1 2 3 4
5 6 7 8
RN1
5.1K
RN1
5.1K
R17 0 R17 0
GND
2
GND
4
GND
6
GND
8
GND
10
TRST#
1
TDI
3
TDO
5
TMS
7
TCK
9
JP1
JTAG
JP1
JTAG
C25
1uF
C25
1uF
1 2 3 4
5 6 7 8
RN2
5.1K RN2
5.1K
R27 NL, 5.1K R27 NL, 5.1K
C39
0.022uF
C39
0.022uF
R16 0 R16 0
C32
0.1uF
C32
0.1uF
TPV38 TPV38
R37
2.26K 1%
R37
2.26K 1%
TPV39 TPV39
R122 150 R122 150
R31 NL, 0 R31 NL, 0
C46
0.1uF
C46
0.1uF
R26 NL, 5.1K R26 NL, 5.1K
C35
0.01uF
C35
0.01uF
NC_PROCMON
F3
STRAP_FAST_BRINGUP#
G2
JTAG_TMS
B10
JTAG_TRST#
B9
JTAG_TCK
C10
JTAG_TDI
A9
JTAG_TDO
A10
PEX_PERST#
G3
EE_CS#
F14
EE_DI
H12
EE_DO
G12
EE_SK
G13
PEX_REFCLKp
J1
PEX_REFCLKn
J2
VSSA_
PL
L
G1
VSS
A1
4
VSS
E6
VSS
E8
VSS
E1
0
V
DD10A
L5
STRAP_TEST_MODE[0]
C11
STRAP_TEST_MODE[1]
B11
STRAP_TEST_MODE[2]
A11
STRAP_TEST_MODE[3]
C12
STRAP_PORTCFG[0]
F13
STRAP_PORTCFG[1]
E14
STRAP_DEBUG_SEL#[1]
A13
STRAP_DEBUG_SEL#[0]
A12
STRAP_UPSTRM_PORT_SEL[0]
A7
STRAP_UPSTRM_PORT_SEL[1]
A6
STRAP_UPSTRM_PORT_SEL[2]
C8
V
DD10A
J3
V
DD10A
L10
VT
T
_
PEX[0
]
L4
VT
T
_
PEX[1
]
L6
VT
T
_
PEX[2
]
L9
V
DD10S
M6
V
DD10S
M8
V
DD10S
M1
0
V
DD10S
M1
2
V
DD10S
M1
4
V
DD10
K8
V
DD10
K4
V
DD10
H10
V
DD10
F10
V
DD10
E9
V
DD10
E5
V
DD33
D9
V
DD33
D10
V
DD33
E4
V
DD33
E1
1
V
DD33
F4
V
DD33
G11
V
DD33
H4
V
DD33A
H3
STRAP_PROBE_MODE#
G14
I2C_SCL
H14
I2C_SDA
H13
I2C_ADDR0
K11
I2C_ADDR1
K12
I2C_ADDR2
L12
FATAL_ERR#
J13
VT
T
_
PEX[3
]
L11
V
DD33
H11
V
DD33
J1
1
V
DD10S
K2
V
DD10S
L3
V
DD10S
L13
V
DD10S
M2
V
DD10S
M4
STRAP_PLL_BYPASS#
F1
V
DD10
E7
V
DD10
G5
V
DD10
J5
V
DD10
K6
V
DD10
K1
0
VSS
F5
VSS
F6
VSS
F7
VSS
F8
VSS
F9
VSS
G6
VSS
G7
VSS
G8
VSS
G9
VSS
G10
VSS
H1
VSS
H2
VSS
H5
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
J4
VSS
J6
VSS
J7
VSS
J8
VSS
J9
VSS
J1
0
VSS
K1
VSS
K3
VSS
K5
VSS
K7
VSS
K1
3
V
DD33
D8
V
DD33
D7
V
DD33
D6
V
DD33
D5
V
DD33
D4
THERMAL_DIODEn
C6
THERMAL_DIODEp
A5
STRAP_SERDES_MODE_EN#
A2
NC_SPARE0
B12
NC_SPARE1
D14
NC_SPARE2
J12
VSS
M3
VSS
L8
VSS
M5
VSS
L2
VSS
M7
VSS
M9
VSS
M1
1
VSS
M1
3
PEX_INTA#
C3
VSS
A1
V
DD33
G4
VSS
J1
4
VSS
K9
V
DD10S
L7
UP STREAM PORT SELECTS
JTAG PORT
EEPROM PORT
PORT CONFIGURATION
TEST MODE SELECT
PLX PEX 8505AA
-PBGA196
I2C PORT
U1B
PEX 8505AA-PBGA196
UP STREAM PORT SELECTS
JTAG PORT
EEPROM PORT
PORT CONFIGURATION
TEST MODE SELECT
PLX PEX 8505AA
-PBGA196
I2C PORT
U1B
PEX 8505AA-PBGA196
GV16 GV16
2 1
D19 Green D19 Green
R11 0 R11 0
1
2
4 3
5
6
ON
SW1
SW SMT-3
ON
SW1
SW SMT-3
R15 0 R15 0
C43
10uF
C43
10uF
R14 0 R14 0
TPV29 TPV29
2 1
D9 Red D9 Red
R25 150 R25 150
R21 5.1K R21 5.1K
C26
0.1uF
C26
0.1uF
SCL
1
GND
2
SDA
3
NC
4
JP4
HEADER 2X2
JP4
HEADER 2X2
C20
10uF
C20
10uF
C21
10uF
C21
10uF
C40
0.022uF
C40
0.022uF
C33
0.1uF
C33
0.1uF
TPV28 TPV28
VCC
8
HOLD#
7
WP#
3
GND
4
CS#
1
SI
5
SO
2
SCK
6
U2
EEPROM Socket
U2
EEPROM Socket
R18 33 R18 33
C47
0.1uF
C47
0.1uF
GV17 GV17
C36
0.01uF
C36
0.01uF
R24 NL, 0 R24 NL, 0
TPV37 TPV37
C44
0.1uF
C44
0.1uF
TPV31 TPV31
C30
10uF
C30
10uF
R35 5.1K R35 5.1K
R32 NL, 0 R32 NL, 0
GV12 GV12
SCL
1
GND
2
SDA
3
NC
4
JP3
HEADER 2X2
JP3
HEADER 2X2
C27
0.1uF
C27
0.1uF
TPV34 TPV34
R34 NL, 0 R34 NL, 0
R20 5.1K R20 5.1K
C42
0.022uF
C42
0.022uF
TPV40 TPV40
R33 5.1K R33 5.1K
C34
0.1uF
C34
0.1uF
GV13 GV13
R12
10K R12
10K
1
2
4 3
5
6
ON
SW2
SW SMT-3
ON
SW2
SW SMT-3
1 2
3 4
5 6
7 8
JP2
HEADER 4X2
JP2
HEADER 4X2
C37
0.01uF
C37
0.01uF
TPV30 TPV30