PLX Technology PEX 8112RDK-F, Hardware Reference Manual

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PEX 8112RDK-F Hardware Reference Manual for Board Revision 1.0, Version 1.1
6 © 2008, PLX Technology, Inc. All rights reserved.
3.5 LED Indicators
The PEX 8112RDK-F provides several LED indicators, including power-on indication and programmable PEX
8112 GPIO lane status indication.
Table 1 provides a quick explanation of each LED indicator.
Table 1. PEX 8112RDK-F LED Indicators
Indicator Type Location LED ON
LED12 12V power is on
LED50
Optional PCI 5V power for
J3 PCI slot
LEDE33 PCI Express 3.3V power is on
LEDP12 PCI 12V power on
LEDP33 PCI 3.3V power is on
LEDP50 PCI 5V power is on
Board Power Indication
LEDVIO VI/O power is on
LED0
Output
OFF (0) – Link Down
ON (1) – Link Up
LED1 Input
LED2 Input
GPIO
LED3 Input
3.6 PEX 8112RDK-F Power
The PEX 8112RDK-F has two sources for DC power. The first source is the card edge connector (J1). This x1
connector provides up to 500 mA at +12V, and 3.0A at +3.3V. Card edge power is intended to power only PEX
8112RDK-F components, as well as optional PCI connector A (J3).
The second source, the 4-pin hard disk power connector, pr12V, -12V, and +5V DC power. The +5V is
converted down to +3.3V and -12V for slots J4, J5, and J6. The +12V power rail is used directly.
3.6.1 PEX 8112 Bridge Device Power
The PEX 8112 bridge device power consists of the following:
ƒ VDD Core +1.5 VDC ±0.1V
ƒ VDD I/O +3.3 VDC ±10%
ƒ VIO Clamp +5 VDC for 5V PCI
+3.3 VDC for 3.3V PCI
3.7 Power Management Signaling
PCI devices assert the PME# pin (connected to the PEX 8112 PMEIN# ball) to signal a Power Management
event. The PEX 8112 converts the PME# signal to PCI Express Power Management Event (PME) messages.
There are no internal events that cause a PME message to be sent upstream.
Power Management messages are used to support PMEs signaled by devices downstream of the PEX 8112.
System software needs to identify the source of a PCI PME reported by a PM_PME message. When the PME
comes from an agent on a PCI Bus, then the PM_PME Message Requester ID reports the Bus Number from
which the PME was collected, and the Device Number and Function Number reported must both be zero (0).
When the PME message is sent to the host, the
PWRMNGCSR
register
PME Status
bit is set and a 100-ms timer
is started. If the status bit is not cleared within 100 ms, another PME message is sent.