EL320.240.36-HB Operations Manual (020-0346-00A)
7
Dimming Connector J2
The J2 analog dimming connector is a Berg six-pin, dual in-line header, part
number 95615-106. The mating connector is the Berg 89947-706 (IDC) or a
combination of the Berg 77138-001 (discrete crimp-to-wire receptacle) and the
Berg 90311-006 (housing). Refer to “Dimming” on page 9 for more
information.
The pin assignments are:
Pin Symbol
Description
1
LUMA
Luminance A
2 GND
Ground
3 RESERVED Reserved
4 LUMC
Luminance
C
5 GND
Ground
6 LUMD
Luminance
D
Interface Information
Planar EL Small Graphics Displays (SGD) incorporate an interface that is similar
to many LCD interfaces. This interface is supported by a variety of
off-the-shelf chip sets which take care of all display control functionality,
freeing the system processor for other tasks. Designers should select the chip
set that best suits their particular architecture and price point.
Video Input Signals
The end of the top line of a frame is marked by VS, vertical sync signal as
shown in Figure 2. The end of each row of data is marked by HS. Depending on
the input frame rate, a continuous low state of the VS input signal will shut the
display scan after one frame period.
Figure 2. Video Input Timing Diagram.
Timing is compatible with LCD graphics controllers.
Pin 1
3
4 5
6
7 8
9
1
2
10
11
Second Line
VID Data
First Line
VID Data
Pixels: a b c d
Pixels: w x y z
HS
VID 0-3
VCLK
HS
VS
Vertical Timing
Horizontal Timing