VSW-1
41
5
6
7
8
5
6
7
8
C
D
F
A
B
E
PEG098A8 (JACK ASSY : IC101)
• System Control Microcomputer
Blockdiagram
Pin layout
V
*
V
V
V
V
V
V
V
V
CL
CC
CC
SS
SS
SS
SS
SS
SS
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
7
6
5
4
3
2
1
0
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
P4 /D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port 3
Port 4
Port 5
P5 /A
P5 /A
P5 /A
P5 /A
3
2
1
0
19
18
17
16
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
P9 /RxD
P9 /RxD
P9 /TxD
P9 /TxD
0
0
DA /AN /P7
DA /AN /P7
AN /P7
AN /P7
AN /P7
AN /P7
AN /P7
AN /P7
7
6
5
4
3
2
1
0
5
4
3
2
1
0
V
AV
AV
REF
CC
SS
CS /P8
ADTRG /CS /IRQ /P8
CS /IRQ /P8
CS /IRQ /P8
IRQ /P8
4
3
1
0
0
0
MD
MD
MD
EXTAL
XTAL
STBY
RES
RESO /FWE
NMI
2
1
0
H8/300H CPU
ROM
15
14
13
12
11
10
9
8
15
14
13
12
11
10
9
8
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
/PA
7
/TP
7
/TIOCB
2
A
20
/PA
6
/TP
6
/TIOCA
2
A
21
/PA
5
/TP
5
/TIOCB
1
A
22
/PA
4
/TP
4
/TIOCA
1
A
23
TCLKD/TIOCB /TP /PA
TCLKC/TIOCA /TP /PA
TCLKB /TP /PA
TCLKA /TP /PA
3
2
0
0
3
2
1
0
1
0
LWR/P6
HWR/P6
RD/P6
AS/P6
BACK/P6
BREQ/P6
WAIT/P6
6
7
5
4
3
2
1
0
RAM
16-bit timer unit
8-bit timer unit
A/D converter
D/A converter
φ
/P6
2
2
2
TP /PB
TP /PB
TP /PB
TP /PB
CS
4
/TMIO /TP /PB
CS
5
/TMO /TP /PB
CS
6
/TMIO /TP /PB
CS
7
/TMO /TP /PB
15
14
7
6
13
10
2
1
9
0
8
11
3
12
5
4
3
2
1
0
P9 /SCK/IRQ
51
P9 /SCK / IRQ
5
4
4
3
1
2
0
1
1
0
3
1
1
3
1
0
Port 1
Programmable
timing pattern
controller (TPC)
(mask ROM or
flash memory)
Interrupt controller
25 24
21
22
23
20 19 18 17 16 15 14 13 12 11
5
8
10
3
9
4
7 6
2
1
100
SDLYB1
SDLYB2
52:
51:
54:N
53:N
77:Vref
76:AVCC
AIN3
AIN4
DA0
AIN2
AIN1
AIN5
PAL/XNT
AVSS
PEG098A8
VSYNC
VSS
VSS
SCK1
SRX1
SRX0
SCK0
STX0
STX1
VSS
FWE
TEST1
HD64F3062BFBL25
SDLYB0
SDLYA2
SDLYA0
SDLYA1
A-SW
B-SW
AUTOSW
XPALSW
XLEDA
LEDAT
XLEDB
N
N
N
N
VSS
N
STBY
φ
VSS
NMI
XRST
VCC
XTAL
EXTAL
CMP-SW
MD1
MD0
NC-SW
VSS
N
XOE
A-FS2IN
A-FS1IN
AIN0
B-FS2IN
B-FS1IN
VCC
MD2
N
75
76
78
77
84
83
80
79
81
82
86
85
87
88
89
91
90
94
92
95
93
97
96
99
98
51 52
55
54
53
58
56 57
59
61 62
60
63 64 65 66 67 68 69
71
70
73
72
74
50
49
48
47
46
44
45
42
43
40
39
41
37
38
35
36
30
29
34
33
31
32
27
28
26
Port 7
Port A
Port B
Port 9
Port 8
Port 6
Port 2
Serial
communication
interface
(SCI )
×
2channels
(WDT)
Watchdog timer
Clock pulse
generator
Bus controller
Address bus
Data bus (upper)
Data bus (lower)
