PDP-5071PU
199
5
6
7
8
5
6
7
8
C
D
F
A
B
E
IN
EN
OUT
FLG
GATE
CONTROL
CURRENT
LIMIT
FLAG
DELAY
UVLO
THERMAL
SHUTDOWN
GND
5
4
1
2
3
1
Pin No.
Name
Function
EN
Enable terminal
GND terminal
FLAG terminal (Open-drain output)
Power input terminal
Output terminal
2
GND
3
FLG
4
IN
5
OUT
R5520H001B (MAIN ASSY : IC7105)
BLOCK DIAGRAM
• USB HIGH-SIDE SW IC
PIN LAYOUT
PIN FUNCTION
Summary of Contents for PDP-5070PU
Page 43: ...PDP 5071PU 43 5 6 7 8 5 6 7 8 C D F A B E ...
Page 47: ...PDP 5071PU 47 5 6 7 8 5 6 7 8 C D F A B E REGULAR AWV2313 AWW1154 ELITE AWV2310 AWW1158 ...
Page 57: ...PDP 5071PU 57 5 6 7 8 5 6 7 8 C D F A B E ...
Page 79: ...PDP 5071PU 79 5 6 7 8 5 6 7 8 C D F A B E 500ns div 500ns div 200ns div ...
Page 200: ...PDP 5071PU 200 1 2 3 4 1 2 3 4 C D F A B E Block Diagram R2S11002AFT MAIN ASSY IC4701 AV SW ...