DRM-ULV16
24
1
2
3
4
1
2
3
4
C
D
F
A
B
E
7.3 IC INFORMATION
LSI53C180-192BGA-K (CONV UNIT: IC901)
• SCSI Expander IC
Retiming
Logic
Precision
Delay
Control
State
Machine
Control
LV
D
DIFFSENS
Receiv
e
r
LVD
DIFFSENS
Receiv
er
SCSI Contr
ol Bloc
k
SCSI Contr
ol Bloc
k
LVD Link T
ransceiv
ers
LVD Link T
ransceiv
e
rs
Control
Signals
LVD, Single-ended,
Wide Ultra SCSI Bus
(A Side)
LVD, Single-ended
Wide Ultra SCSI Bus
(B Side)
A_DIFFSENS
B_DIFFSENS
40 MHz Clock Input
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC
VDD
IO
NC
NC
NC
XFER_ACTIVE
RESET/
A_DIFFSENS
A_SD12-
B1
B2
B3
B4
B5
B6
B7
B8
B9
B_SD11-
NC
NC
WS_ENABLE/
BSY_LED
NC
VDD
CORE
C1
C2
C3
C4
C5
C6
C7
C8
C9
B_SD10-
B_DIFFSENS
NC
VDD
SCSI
NC
VSS
CLOCK
VDD
SCSI
D1
D2
D3
B_SD9+
B_SD9-
NC
E1
E2
E3
B_SD8+
B_SD8-
VDD
SCSI
F1
F2
F3
B_SIO+
B_SIO-
NC
G1
G2
G3
G7
G8
G9
B_SREQ-
VSS
VSS
VSS
VSS
H1
H2
H3
H7
H8
H9
B_SCD-
B_SCD+
VSS
VSS
VSS
J1
J2
J3
J7
J8
B_SSEL-
VDD
SCSI
VSS
VSS
K1
K2
K3
K7
K8
K9
B_SMSG-
VDD
CORE
VSS
VSS
VSS
L1
L2
L3
L7
L8
L9
B_SRST-
NC
VSS
VSS
VSS
VSS
M1
M2
M3
B_SACK-
N1
N2
N3
B_SBSY-
VDD
SCSI
P1
P2
P3
B_SATN-
B_SDP0-
R1
R2
R3
R4
R5
R6
R7
R8
R9
B_RBIAS
B_SD7+
B_SD7-
NC
VDD
SCSI
B_SD2+
VSS
B_SD0-
VDD
SCSI
T1
T2
T3
T4
T5
T6
T7
T8
T9
NC
B_SD6+
B_SD5+
B_SD4+
B_SD3+
B_SD2-
B_SD1+
B_SD0+
U1
U2
U3
U4
U5
U6
U7
U8
U9
NC
B_SD6-
B_SD5-
B_SD4-
B_SD3-
NC
B_SD1-
VDD
CORE
B_SDP1-
A10
A11
A12
A13
A14
A15
A16
A17
A_SD13-
A_SD0-
A_SD1-
A_SD2-
A_SD3-
NC
B10
B11
B12
B13
B14
B15
B16
B17
A_SD14-
A_SD15-
A_SDP1-
A_SD0+
A_SD1+
A_SD2+
A_SD3+
A_SD4-
C10
C11
C12
C13
C14
C15
C16
C17
VSS
VDD
SCSI
NC
NC
A_SD5-
A_SD4+
D15
D16
D17
A_SD5+
A_SD6+
A_SD6-
E15
E16
E17
VDD
SCSI
A_SD7+
A_SD7-
F15
F16
F17
NC
A_SDP0-
G10
G11
G15
G16
G17
VSS
VSS
VSS
A_SATN-
H10
H11
H15
H16
H17
VSS
VSS
NC
A_SBSY-
J10
J11
J15
J16
J17
VSS
VSS
VDD
A_SACK-
K10
K11
K15
K16
K17
VSS
VSS
VDD
CORE
A_SRST-
A_RBIAS
L10
L11
L15
L16
L17
VSS
VSS
VSS
A_SMSG-
M15
M16
M17
A_SSEL-
N15
N16
N17
VDD
SCSI
A_SCD+
A_SCD-
P15
P16
P17
NC
A_SREQ-
R10
R11
R12
R13
R14
R15
R16
R17
NC
VSS
NC
VDD
SCSI
A_SD9-
A_SIO+
A_SIO-
T10
T11
T12
T13
T14
T15
T16
T17
A_SD10-
A_SD8+
A_SD8-
U10
U11
U12
U13
U14
U15
U16
U17
B_SD15-
B_SD14-
B_SD13-
B_SD12-
A_SD11-
A_SD9+
NC
NC
A_SSEL-
A_SBSY-
A_SRST-
A_SREQ-
A_SACK-
A_SMSG-
A_SCD+
A_SCD-
A_SIO+
A_SIO-
A_SATN-
A_SDP[1:0]+
A_SDP[1:0]-
A_SD[15:0]+
A_SD[15:0]-
A_DIFFSENS
B_SSEL-
B_SBSY-
B_SRST-
B_SREQ-
B_SACK-
B_SMSG-
B_SCD+
B_SCD-
B_SIO+
B_SIO-
B_SATN-
B_SDP[1:0]+
B_SDP[1:0]-
B_SD[15:0]+
B_SD[15:0]-
B_DIFFSENS
A Side
LVD or SE
SCSI Interface
B Side
LVD or SE
SCSI Interface
Control Signals
LSI53C180
RESET/
WS_ENABLE
BSY_LED
XFER_ACTIVE
CLOCK
A_RBIAS
B_RBIAS
Pin Arrangement (Top view)
Block diagram
• The information shown in the list is basic information and may not correspond exactly to that shown in the schematic diagrams.