Pioneer DBR-T210GBN, Service Manual

Page: 56 / 65

56
DBR-T210GBS, DBR-T210GBP
DBR-T210GBN
•
Pin Function (1/3)
POWER
NAME PIN TYPE DESCRIPTION
GND 1 I System ground
VDD 16 I Power supply input, 5 V
±
10% (73K324BL). Bypass with 0.1
and 22
µ
F capacitors to GND.
VREF 31 O An internally generated reference voltage. Bypass with 0.1
µ
F
capacitor to ground.
ISET 28 I Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 M
Ω
resistor. ISET should be bypassed to GND with a
0.1
µ
F capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE 13 I ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on &6 .
AD0-AD7 5-12 I/O ADDRESS/DATA BUS: These bi-directional tri-state
multiplexed lines carry information to and from the internal
registers.
CS
23 I CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if CS
(latched) is not active. The state of CS is latched on the falling
edge of ALE.
CLK 2 O OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the crystal
frequency on reset.
INT
20 O INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt. INT will stay low until the processor
reads the detect register or does a full reset.
RD
15 I READ: A low requests a read of the 73K324BL internal
registers. Data can not be output unless both RD and the
latched CS are active or low.
RESET 30 I RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.