Pioneer DBR-T210GBN, Service Manual

Page: 45 / 65

45
DBR-T210GBS, DBR-T210GBP
DBR-T210GBN
•
Pin Function (3/5)
Pin In/Out Function
MemAddr2-23 out Address bus
MemData0-31 in/out Data bus. MemData0 is the least significant bit (LSB) and
MemData31
is the most
significant bit (MSB).
MemRdnotWr out ReadnotWrite strobe
MemReq in Direct memory access request
MemGrant out Direct memory access granted
MemWait i n Memory cycle extender
notMemCAS0,2 out CAS strobes for SDRAM/DRAM in Banks 0 and 1
notMemCAS1 out CAS strobe for DRAM or SDRAM clock
notMemCAS3 out CAS strobe for DRAM or sub-bank chip select for bank 3
notMemRAS0 out RAS strobe for SDRAM/DRAM in Bank 0, chip select for Bank0 or
RAS strobe for lowest DRAM sub-bank in Bank0
notMemRAS1 out RAS strobe for highest DRAM sub-bank in Bank0 or
SDRAM Chip select signal for highest sub-bank of Bank0
notMemRAS2 out RAS strobe for SDRAM/DRAM in bank 1, chip select for Bank1 or
RAS strobe for lowest DRAM sub-bank in Bank1
notMemRAS3 out RAS strobe for highest DRAM sub-bank in Bank1 or
SDRAM Chip select signal for Bank1
notMemCSROM out Chip select strobe for ROM in bank3.
notSDRAMCS0 out SDRAM Chip select signal for Bank0 or lowest sub-bank of Bank0
notMemOE out Output enable strobe - banks 0-3.
notMemBE0-3 out Byte enable strobes - banks 0-3.
notMemCS2 out Chip select strobe for memory in bank 2.
BootSource0-1 in Boot from ROM or from link.
ProcClockOut out Processor clock.
Table 6 STi5512 External memory interface pins
Pin In/Out Function
AD0-12 out SDRAM address bus
DQ0-15 in/out SDRAM data bus (lower byte)
notSDCS0 out SDRAM chip select for first SDRAM
notSDCS1/AD13 out SDRAM chip select for second SDRAM or AD13
notSDCAS out SDRAM CAS
notSDRAS out SDRAM RAS
notSDWE out SDRAM write enable
MEMCLKIN in SDRAM memory clock input
MEMCLKOUT out SDRAM memory clock output
DQML out DQ mask enable (lower)
DQMU out DQ mask enable (upper)
Table 7 Shared SDRAM interface pins