CX-3168
16
1
2
3
4
1
2
3
4
C
D
F
A
B
E
1.5 STS CIRCUIT EXPLANATION
Sure Track System circuit pools music data read from CD, and when pick up is out of the track by some reasons, it
outputs data from memory during recovery and prevents sound break effectively.
Operation theory
STS circuit is controlled by uPD63761AGJ (IC201) having a built-in shockproof memory controller. Signal read from
CD with double rate is demodulated to data in CDLSI, and the built-in memory controller memorizes SDRAM audio
data, then reads out SDRAM data with single rate based on the output clock from C33M port of the LSI (33.86MHz)
as reference clock, and outputs DAC.
Since the writing speed is faster than the reading speed from SDRAM, the memory may overflow soon. However, if
it overflows, reading is stopped temporarily and to be in pause. Reading data from SDRAM continues and when
empty space is available, writing data is restarted. (Remaining RAM can be monitored by "RAM0, RAM1 and
RAM2" terminal.)
By repeating this process, SDRAM is always utilized effectively and data during 12 seconds (at the time of CD-DA)
can be stored. For example, pick up is out of the track because of vibration, sound break is avoided if recovery is
performed within 12 seconds by using memory.
Compact Disk
CD LSI
(RF Amp./Servo DSP/
Signal Processor/
Audio DAC/LPF)
IC201
UPD63763AGJ,UPD63761AGJ
16M DRAM/IC202
MSM56V16160 F8TKFM
x2 Data Read
Double Rate
Single Rate
x1 Playback
3.3V system
V3R3
Analog Audio
DAC+LPF
