16
CDJ-2000NXS
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A
B
C
D
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F
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5. DIAGNOSIS
5.1 POWER ON SEQUENCE
Power on
Power on
Pin Y22 of Main CPU
(IC101) cancels reset
at H.
Program transfer from
FLASH to SDRAM
Canceling DSP reset
from pin B1
8
of Main
CPU. Pin G2 of DSP
(IC501) becomes "H".
Canceling ETH_PHY reset
from pin A1
8
of Main
CPU. Pin 42 of ETH_PHY
(IC1304) becomes "H".
Canceling USB_B reset
from pin A17 of Main
CPU. Pin 46 of USB_B
(IC1101) becomes "H".
Canceling ATAPI reset
from pin C10 of Main
CPU. Pin 173 of SODC
(IC7006) becomes "H".
Program transfer to
DSP
Register setting of ETH_PHY
Register setting of USB_B
Initialization of the
built-in peripherals
Initialization of the SDRAM
Initialization of the SDRAM
Initialization of the DSP
Initialization of the DAC
Initialization of the per
ipher
al de
vice
Initialization of the Main CPU
Pin 13 of TFT CPU
(IC4001) cancels reset
at H.
Program transfer from
FLASH to SDRAM
Pin 12 of P
N
L CPU
(IC
8
003) cancels reset
at H.
Pin 45 of SODC
(IC7006) cancels reset
at H.
Initialization of the SDRAM
Initialization of the TFT CPU
Display an opening screen
Initialization of the
peripheral device
Power on
Initialization of the JOG_FL
Initialization of the P
N
L CPU
Initialization of the CDC
Power on
Initialization of the
loading mechanism
Initialization of the ATAPI
LED initial lighting
Device select screen
Canceling reset
Apple authentication chip
Communication between Main CPU and SR
V
O
Initialization of the SODC
The insertion of the
disk is possible.
The insertion of the
disk is possible.
Built-in peripherals
• USB_A
• ETH_MAC
• SD
• ATAPI
• SERIAL
• SSI
Communication between Main CPU and P
N
L CPU
Communication between Main CPU and TFT CPU
MAIN CPU
TFT CPU
PANEL CPU
SRVO
