Philips Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B Specification Download Page 18

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Philips Semiconductors

TDA8752B

Triple high-speed Analog-to-Digital Converter 110 Msps

Product specification

Rev. 03 — 21 July 2000

18 of 38

9397 750 07338

The default programmed value is:

•

Programmed code = 127

•

Clamp code = 0

•

ADC output = 0.

9.1.2

Coarse and fine registers

These two registers enable the gain control, the AGC gain with the coarse register
and the reference voltage with the fine register. The coarse register programming
equation is as follows:

(5)

Where: V

ref

= 2.5 V.

The gain correspondence is given in

Table 6

. The gain is linear with reference to the

programming code (N

FINE

= 0).

The default programmed value is as follows:

•

COARSE

= 32

•

Gain = 0.825

•

to be full-scale = 1.212 V.

To modulate this gain, the fine register is programmed using the above equation. With
a full-scale ADC input, the fine register resolution is a

⁄

LSB peak-to-peak

(see

Table 7

for N

COARSE

= 32).

Table 5:

Coding

Programmed code

Clamp code

ADC output

−

63.5

underflow

−

62.5

...

127

...

254

63.5

63 or 64

255

256

120

...

287

136

Table 6:

Gain correspondence (COARSE)

COARSE

Gain

to be full-scale (V)

0.825

1.212

2.5

0.4

GAIN

COARSE

ref

FINE

------------------

–









⋅

------------------------------------------------

------

COARSE

ref

512

FINE

–

(

)

⋅

--------------------------------------------------

Summary of Contents for Triple high-speed Analog-to-Digital Converter 110 Msps TDA8752B

Page 1: ...s interface for example two ICs used in an odd even configuration 2 Features Triple 8 bit ADC Sampling rate up to 110 Msps IC controllable via a serial interface which can be either I2C bus or 3 wire serial bus selected via a TTL input pin IC analog voltage input from 0 4 to 1 2 V p p to produce a full scale ADC input of 1 V p p Three clamps for programming a clamping code between 63 5 and 64 in s...

Page 2: ...75 5 0 5 25 V VCCO output stages supply voltage for R G and B channels 4 75 5 0 5 25 V VCCA PLL analog PLL supply voltage 4 75 5 0 5 25 V VCCO PLL output PLL supply voltage 4 75 5 0 5 25 V ICCA analog supply current 120 mA IDDD logic supply current for I2C bus and 3 wire 1 0 mA ICCD digital supply current 40 mA ICCO output stages supply current fclk 110 MHz ramp input 26 mA ICCA PLL analog PLL sup...

Page 3: ...r ratio 100 4095 Ptot total power dissipation fclk 110 MHz ramp input 1 1 W jPLL rms maximum PLL phase jitter RMS value fref 66 67 kHz fclk 110 MHz 112 ps Table 1 Quick reference data continued Symbol Parameter Conditions Min Typ Max Unit Table 2 Ordering information Type number Package Sampling frequency MHz Name Description Version TDA8752BH 8 QFP100 plastic quad flat package 100 leads lead leng...

Page 4: ... BCLP RBOT RCLP GBOT GCLP DEC2 DEC1 HSYNC n c HSYNCI ADD2 BIN BGAINC BAGC GAGC Vref RDEC RIN RGAINC RAGC GDEC GIN GGAINC BDEC ADD1 SEN SCL SDA DIS BLUE CHANNEL GREEN CHANNEL TDA8752B RED CHANNEL ADC GOR ROR MUX CLAMP OUTPUTS 6 VCCA R 11 VCCA G 19 VCCA B 27 VDDD 40 AGNDG 21 VCCO G 69 VCCO B 59 VCCO R 79 VCCD 95 VCCA PLL 99 VCCO PLL 85 CLP 89 AGNDR 13 VSSD 41 AGNDB 29 OGNDG 60 OGNDR 70 AGNDPLL 96 OG...

Page 5: ...ps Electronics N V 2000 All rights reserved Fig 2 Red channel diagram 150 kΩ RIN VP VCCAR RCLP CLP RAGC CLKADC Vref 3 kΩ 45 kΩ DAC 5 DAC ROR R0 to R7 OE RBOT RGAINC HSYNCI ADC D R D R REGISTER I2C BUS FCE468 OUTPUTS MUX AGC CLAMP CONTROL REGISTER FINE GAIN ADJUST I2C bus 5 bits Fr I2C bus 7 bits Cr I2C bus 8 bits Or REGISTER COARSE GAIN ADJUST 1 8 8 7 8 1 8 ...

Page 6: ...PHASE FREQUENCY DETECTOR I2C bus 5 bits Ip Up Do I2C bus 1 bit Vlevel I2C bus 12 bits Di I2C bus 1 bit Ckb phase selector A I2C bus 5 bits Pa I2C bus 1 bit Cka I2C bus 1 bit Ckab edge selector I2C bus 1 bit Edge CLKADC I2C bus 2 bits Vco CZ loop filter I2C bus 3 bits Z 12 to 100 MHz DIV N 100 to 4095 0 180 MUX SYNCHRO MUX MUX NCKBO CP CZ CP COAST CKEXT INV VCO CKADCO CKAO CKREFO CKREF phase select...

Page 7: ...3 2 1 n c AGNDB BIN VCCA B BDEC BCLP BGAINC BBOT BAGC AGNDG GIN VCCA G GDEC GCLP GGAINC GBOT GAGC AGNDR RIN VCCA R RDEC RCLP RGAINC RBOT RAGC n c DEC1 Vref DEC2 n c n c B1 B2 B3 B4 B5 B6 B7 VCCO B OGNDG G0 G1 G2 G3 G4 G5 G6 G7 VCCO G OGNDR R0 R1 R2 R3 R4 R5 R6 R7 VCCO R CKREFO 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 n c V CCA PLL CZ CP AGND PLL V CCD CKREF COAST CKEXT INV HSYN...

Page 8: ...put BOT GGAINC 16 green channel gain capacitor input GCLP 17 green channel gain clamp capacitor input GDEC 18 green channel gain regulator decoupling input VCCA G 19 green channel gain analog power supply GIN 20 green channel gain analog input AGNDG 21 green channel gain analog ground BAGC 22 blue channel AGC output BBOT 23 blue channel ladder decoupling input BOT BGAINC 24 blue channel gain capac...

Page 9: ... 3 B4 55 blue channel ADC output bit 4 B5 56 blue channel ADC output bit 5 B6 57 blue channel ADC output bit 6 B7 58 blue channel ADC output bit 7 MSB VCCO B 59 blue channel ADC output power supply OGNDG 60 green channel ADC output ground G0 61 green channel ADC output bit 0 LSB G1 62 green channel ADC output bit 1 G2 63 green channel ADC output bit 2 G3 64 green channel ADC output bit 3 G4 65 gre...

Page 10: ... output power supply DGND 86 digital ground OE 87 output enable active LOW when OE is HIGH the outputs are in high impedance PWDWN 88 power down control input device is in Power down mode when this pin is HIGH CLP 89 clamp pulse input clamp active HIGH HSYNC 90 horizontal synchronization input pulse INV 91 PLL clock output inverter command input invert when HIGH CKEXT 92 external clock input COAST...

Page 11: ...ternal TTL positive going pulse pin CLP The drop of the video signal is 1 LSB Normally the circuit operates with a 0 code clamp corresponding to the 0 ADC code This clamp code can be changed from 63 5 to 64 as represented in Figure 5 in steps of 1 2 LSB The digitized video signal is always between code 0 and code 255 of the ADC It is also possible to clamp from code 120 to code 136 corresponding t...

Page 12: ...ceive data via a serial interface to enable the gain to be programmed The preset value loaded in the 7 bit register is chosen between approximately 67 codes to ensure the full scale input range see Figure 6 A contrast control can be achieved using these registers In this case care should be taken to stay within the allowed code range 32 to 99 A fine correction using three 5 bit DACs also controlle...

Page 13: ...he timing must be checked very carefully if the capacitive load is more than 10 pF 8 6 Phase locked loop The ADCs are clocked either by an internal PLL locked to the CKREF clock all of the PLL is on chip except the loop filter capacitance or by an external clock applied to pin CKEXT Selection is performed via the serial interface bus The reference clock CKREF range is between 15 and 280 kHz Conseq...

Page 14: ...is available on Philips Semiconductor Internet site to calculate the best PLL parameters It is possible to control independently the phase of the ADC clock and the phase of an additional clock output which could be used to drive a second TDA8752B For this two serial interface controlled digital phase shift controllers are included controlled by 5 bit registers phase shift controller steps are 11 2...

Page 15: ...the TDA8752B master and CKAO to the slave TDA8752B In this case on pin CKAO CKBO will be the output with bit CKAB of the master at logic 1 The master TDA8752B is used to sample the even pixels and the slave TDA8752B for odd pixels using a 180 deg phase shift between the clocks both pins CKADCO The master chip and the slave chip have their pin INV LOW which guarantees the 180 deg shift ADC clock dr...

Page 16: ...erface All programming is described in Section 9 I2C bus and 3 wire serial bus interfaces Slave at 180 deg phase shift with respect to pin CKADCO of the master TDA8752B Fig 9 Dual TDA8752B solution for pixel clock rate with a single phase adjustment 100 to 200 MHz FCE466 I2C bus 1 bit Ckb Ckb 1 phase selector A I2C bus 5 bits Pa I2C bus 1 bit Cka Cka 1 CLKADC 12 to 100 MHz PLL Master TDA8752B even...

Page 17: ...or the RGB channels The relationship between the programming code and the level of the clamp code is given in Table 5 Table 4 I2C bus and 3 wire serial bus registers Function name Subaddress Bit definition Default value A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB SUBADDR X X X Mode Sa3 Sa2 Sa1 Sa0 XXX1 0000 OFFSETR X X X X 0 0 0 0 Or7 Or6 Or5 Or4 Or3 Or2 Or1 Or0 0111 1111 COARSER X X X X 0 0 0 1 Or8 Cr6 Cr5 C...

Page 18: ...Vref 2 5 V The gain correspondence is given in Table 6 The gain is linear with reference to the programming code NFINE 0 The default programmed value is as follows NCOARSE 32 Gain 0 825 Vi to be full scale 1 212 V To modulate this gain the fine register is programmed using the above equation With a full scale ADC input the fine register resolution is a 1 2 LSB peak to peak see Table 7 for NCOARSE ...

Page 19: ...it is at logic 1 The bits Up and Do are used for the test to force the charge pump current These bits have to be logic 0 during normal use The bits Ip0 Ip1 and Ip2 control the charge pump current to increase the bandwidth of the PLL as shown in Table 8 The default programmed value is as follows Charge pump current 100 µA Test bits no test mode bits Up and Do at logic 0 Rising edge of CKREF bit Edg...

Page 20: ...e bits Vco1 and Vco0 control the VCO gain The default programmed value is as follows Internal resistance 16 kΩ VCO gain 15 MHz V Table 9 VCO register bits Z2 Z1 Z0 Resistance kΩ 0 0 0 high impedance 0 0 1 128 0 1 0 32 0 1 1 16 1 0 0 8 1 0 1 4 1 1 0 2 1 1 1 1 Table 10 VCO gain control Vco1 Vco0 VCO gain MHz V Pixel clock frequency range MHz 0 0 15 10 to 20 0 1 20 20 to 40 1 0 35 40 to 70 1 1 50 70 ...

Page 21: ...sters are set to their default values in that event they have to be reprogrammed if the required settings are different e g through an EEPROM When the device is in Power down mode the previously programmed register values remain unaffected 9 1 7 PHASEA and PHASEB registers Bit Cka is logic 0 when the used clock is the PLL clock and logic 1 when the used clock is the external clock Bit Ckb is logic...

Page 22: ...st always be equal to logic 0 because it is not possible to read the data in the register The timing and protocol for the I2C bus are standard Two sequences are available see Table 13 and 14 Table 12 I2C bus address A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 1 ADD2 ADD1 0 Table 13 Address sequence for mode 0 Where S START condition ACK acknowledge and P STOP condition S IC ADDRESS ACK SUBADDRESS REGISTER1 AC...

Page 23: ...rst byte refers to the register address which is programmed The second byte refers to the data to be sent to the chosen register see Table 4 The acquisition is achieved via SEN Using the 3 wire serial bus interface an indefinite number of ICs can operate on the same system Pin SEN is used to validate the circuits Fig 10 3 wire serial bus protocol FCE474 ts3W 100 ns th3W 100 ns tr3W 600 ns 100 ns 1...

Page 24: ...pin OE 1 0 mA II PWDWN input current pin PWDWN 1 0 mA Tstg storage temperature 55 150 C Tamb ambient temperature 0 70 C Tj junction temperature 150 C Table 16 Thermal characteristics Symbol Parameter Conditions Value Unit Rth j a thermal resistance from junction to ambient in free air 52 K W Table 17 Characteristics VCCA V11 or V19 V27 or V99 referenced to AGND V13 V21 V29 or V96 4 75 to 5 25 V VC...

Page 25: ...register code 32 see Figure 6 1 67 dB maximum coarse gain register code 99 see Figure 6 8 dB GFINE fine gain correction range fine register input code 0 see Figure 7 0 dB fine register input code 31 see Figure 7 0 5 dB Gamp T amplifier gain stability as a function of temperature Vref 2 5 V with 100 ppm C maximum variation 200 ppm C IGC gain current 20 µA tstab amplifier gain adjustment speed HSYNC...

Page 26: ...er input code 398 136 LSB Phase locked loop jPLL rms maximum PLL phase jitter RMS value fclk 110 MHz see Table 18 112 ps DR divider ratio 100 4095 fref reference clock frequency range 15 280 kHz fPLL output clock frequency range 12 110 MHz tCOAST max maximum coast mode time 40 lines trecap PLL recapture time when coast mode is aborted 3 lines tcap PLL capture time in start up conditions 5 ms Φstep...

Page 27: ... 5 10 1 10 7 ns INV set to HIGH 10 1 1 2tclk ns t td CLKO time difference between samples when operated in the same supply and temperature conditions 0 1 0 3 ns Data timing see Figure 11 fclk 110 MHz CL 10 pF 2 td s sampling delay time referenced to CKADCO ns td o output delay time 2 1 5 ns th o output hold time 1 5 2 3 ns 3 state output delay time see Figure 12 tdZH output enable HIGH 12 ns tdZL ...

Page 28: ...time of the chip before 3 wire serial bus communication 600 ns tsu data set up time 100 ns th data hold time 100 ns I2C bus 4 fSCL clock frequency 0 100 kHz tBUF time the bus must be free before new transmission can start 4 7 µs tHD STA start condition hold time 4 0 µs tSU STA start condition set up time repeated start 4 7 µs tCKL LOW level clock period 4 7 µs tCKH HIGH level clock period 4 0 µs t...

Page 29: ...imings are given for a 10 pF capacitive load A higher load can be used but the timing must then be rechecked 3 The input current must be limited in accordance with the limiting values 4 The I2C bus timings are given for a frequency of 100 kbit s 100 kHz This bus can be used at a frequency of 400 kbit s 400 kHz Fig 11 Data timing diagram td s sample N 1 sample N 2 sample N CKADCO n FCE475 50 1 4 V ...

Page 30: ...VCCD VCCO 5 V Tamb 25 C Video standards fref kHz fclk MHz N KO MHz V CZ nF CP nF IP µA Z kΩ Long term time jitter 1 RMS value ps peak to peak value ns CGA 640 200 15 75 14 3 912 15 39 0 15 100 8 593 3 56 VGA 640 480 31 5 25 18 800 20 39 0 15 200 4 255 1 53 VGA 640 482 48 07 38 4 800 20 39 0 15 400 4 173 1 04 VESA 800 600 SVGA 72 Hz 48 08 50 1040 35 39 0 15 200 4 200 1 2 VESA 1024 768 XGA 75 Hz 60 ...

Page 31: ... CKREFO VCCO R R7 R6 R5 R4 R3 R2 R1 R0 R1 R2 OGNDR VCCO G G7 G6 G5 G4 G3 G2 G1 G0 OGNDG VCCO B B7 B6 B5 B4 B3 B2 B1 n c DEC2 Vref DEC1 n c RAGC RBOT RGAINC RCLP RDEC VCCA R RIN AGNDR GAGC GBOT GGAINC GCLP GDEC VCCA G GIN AGNDG BAGC BBOT BGAINC BCLP BDEC VCCA B BIN RIN 2 5 V GIN BIN AGNDB n c n c VCCA PLL CZ CP AGNDPLL VCCD CKREF COAST CKEXT INV HSYNC CLP PWDWN OE DGND VCCO PLL CKADCO CKBO OGNDPLL ...

Page 32: ... EIAJ mm 0 25 0 05 2 90 2 65 0 25 0 40 0 25 0 25 0 14 14 1 13 9 0 65 18 2 17 6 1 0 0 6 7 0 o o 0 15 0 1 0 2 1 95 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included 1 0 0 6 SOT317 2 MO 112 97 08 01 99 12 27 D 1 1 1 20 1 19 9 HD 24 2 23 6 E Z 0 8 0 4 D e θ E A1 A Lp detail X L A 3 B 30 c bp E H A2 D ZD A ZE e v M A 1 100 81 80 5...

Page 33: ...ng or pressure syringe dispensing before package placement Several methods exist for reflowing for example convection or convection infrared heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferab...

Page 34: ...g upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 2 These packages are not suitable f...

Page 35: ...roduct specification Rev 03 21 July 2000 35 of 38 9397 750 07338 Philips Electronics N V 2000 All rights reserved 17 Revision history Table 20 Revision history Rev Date CPCN Description 3 20000721 Product specification 2 20000110 Preliminary specification 1 19991111 Objective specification ...

Page 36: ... such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconducto...

Page 37: ... 27 09 1415 Malaysia Tel 60 37 50 5214 Fax 60 37 57 4880 Mexico Tel 9 5 800 234 7381 Middle East see Italy Netherlands Tel 31 40 278 2785 Fax 31 40 278 8399 New Zealand Tel 64 98 49 4160 Fax 64 98 49 7811 Norway Tel 47 22 74 8000 Fax 47 22 74 8341 Philippines Tel 63 28 16 6380 Fax 63 28 17 3474 Poland Tel 48 22 5710 000 Fax 48 22 5710 001 Portugal see Spain Romania see Italy Russia Tel 7 095 755 6...

Page 38: ...7 Pinning information 7 7 1 Pinning 7 7 2 Pin description 8 8 Functional description 11 8 1 IC analog video inputs 11 8 2 Clamps 11 8 3 Variable gain amplifiers 11 8 4 ADCs 13 8 5 ADC outputs 13 8 6 Phase locked loop 13 8 7 I2C bus and 3 wire serial bus interface 16 9 I2C bus and 3 wire serial bus interfaces 17 9 1 Register definitions 17 9 1 1 Offset register 17 9 1 2 Coarse and fine registers 18...

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