Philips SC28L91 Product Data Sheet Download Page 9

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Philips Semiconductors

Product data sheet

SC28L91

3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)

2004 Oct 21

PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA



)

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

Symbol

ÁÁÁ

Pin
type

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Name and function

ÁÁÁÁ

I/M

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Bus Configuration: When low configures the bus interface to the Conditions shown in this table.

ÁÁÁÁ

D0–D7

ÁÁÁ

I/O

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the
CPU. D0 is the least significant bit.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

CEN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on
D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.

ÁÁÁÁ

R/WN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.

ÁÁÁÁ

IACKN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in
response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

DACKN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to
indicate proper transfer of data between the CPU and the UART.

ÁÁÁÁ

A0–A3

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Address Inputs: Select the UART internal registers and ports for read/write operations.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

RESETN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,
stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets
MR pointer to MR1. See Figure 4

ÁÁÁÁ

INTRN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable
interrupting conditions are true. This pin requires a pullup.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

X1/CLK

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When
a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).

ÁÁÁÁ

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this
pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.

ÁÁÁÁ

RxD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

TxD

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition
when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.

ÁÁÁÁ

OP0

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on
receive or transmit.

ÁÁÁÁ

OP1

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 1: General-purpose output.

ÁÁÁÁ

OP2

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.

ÁÁÁÁ

OP3

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 3: General purpose output.

ÁÁÁÁ

OP4

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control

ÁÁÁÁ

OP5

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 5: General-purpose output.

ÁÁÁÁ

OP6

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control

ÁÁÁÁ

OP7

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output 7: General-purpose output.

ÁÁÁÁ

IP0

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.

ÁÁÁÁ

IP1

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 1: General purpose input. Has Change of State Dector.

ÁÁÁÁ

IP2

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.

ÁÁÁÁ

IP3

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-

mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.

ÁÁÁÁ

ÁÁ

ÁÁÁÁ

IP4

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,

the received data is sampled on the rising edge of the clock.

ÁÁÁÁ

IP5

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input 5: General purpose input.

ÁÁÁÁ

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power Supply: +3.3 or +5V supply input

10%

ÁÁÁÁ

GND

ÁÁÁ

Pwr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Ground

Summary of Contents for SC28L91

Page 1: ... SC28L91 3 3 V or 5 0 V Universal Asynchronous Receiver Transmitter UART Product data sheet Supersedes data of 2000 Sep 22 2004 Oct 21 INTEGRATED CIRCUITS ...

Page 2: ...bility is provided via RTS CTS signaling to disable a remote transmitter when the receiver buffer is full DMA interface is and other general purpose signals are provided on the SC28L91 via a multipurpose 7 bit input port and a multipurpose 8 bit output port These can be used as general purpose ports or can be assigned specific functions such as clock inputs or status interrupt outputs FIFO conditi...

Page 4: ... 29 RxDA 30 x1 clk Pin Function 31 x2 32 RESET 33 CEN 34 IP2 35 IP6 36 IP5 37 IP4 38 VCC 39 VCC 40 A0 41 IP3 42 A1 43 IP1 44 A2 PQFP 44 34 1 11 33 23 12 22 SD00698 1 39 17 28 40 29 18 7 PLCC 6 SD00699 Pin Function 1 NC 2 A0 3 IP3 4 A1 5 IP1 6 A2 7 A3 8 IP0 9 WRN 10 RDN 11 VCC 12 I M 13 No Connection 14 OP1 15 OP3 Pin Function 16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 VSS 23 NC 24 INTRN 25 D6 26 D4 ...

Page 5: ... RxDA 30 x1 clk Pin Function 31 x2 32 RESETN 33 CEN 34 IP2 35 IACKN 36 IP5 37 IP4 38 VCC 39 VCC 40 A0 41 IP3 42 A1 43 IP1 44 A2 PQFP 44 34 1 11 33 23 12 22 SD00700 1 39 17 28 40 29 18 7 PLCC 6 SD00701 Pin Function 1 NC 2 A0 3 IP3 4 A1 5 IP1 6 A2 7 A3 8 IP0 9 R WN 10 DACKN 11 VCC 12 I M 13 No Connection 14 OP1 15 OP3 Pin Function 16 OP5 17 OP7 18 D1 19 D3 20 D5 21 D7 22 VSS 23 NC 24 INTRN 25 D6 26 ...

Page 6: ...PT CONTROL IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER TIMER XTAL OSC CSR ACR CTL DATA CHANNEL 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE FIFO MRA0 1 2 CRA SRA INPUT PORT CHANGE OF STATE DETECTORS 4 OUTPUT PORT FUNCTION SELECT LOGIC OPCR TxDA RxDA IP0 IP6 OP0 OP7 VCC VSS CONTROL TIMING INTERNAL DATABUS IPCR ACR OPR CTU 8 7 WATCH DOG TIMER RECEIVE SHIFT REGISTER SD...

Page 7: ...ROL IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER TIMER XTAL OSC CSR ACR CTL DATA CHANNEL 16 BYTE TRANSMIT FIFO TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE FIFO MRA0 1 2 CRA SRA INPUT PORT CHANGE OF STATE DETECTORS 4 OUTPUT PORT FUNCTION SELECT LOGIC OPCR TxDA RxDA IP0 IP5 OP0 OP7 VCC VSS CONTROL TIMING INTERNAL DATABUS IPCR ACR OPR CTU 8 6 WATCH DOG TIMER RECEIVE SHIFT REGISTER SD00703 I...

Page 8: ...n to ground see Figure 11 X2 O Crystal 2 Connection for other side of the crystal When a crystal is used a capacitor must be connected from this pin to ground see Figure 11 If X1 CLK is driven from an external source this pin must be left open RxD I Receiver Serial Data Input The least significant bit is received first Mark is High space is Low TxD O Transmitter Serial Data Output The least signif...

Page 9: ... side of the crystal When a crystal is used a capacitor must be connected from this pin to ground see Figure 11 If X1 CLK is driven from an external source this pin must be left open ÁÁÁÁ ÁÁÁÁ RxD ÁÁÁ ÁÁÁ I ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Receiver Serial Data Input The least significant bit is received first Mark is High space is Low ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ TxD ÁÁÁ ÁÁÁ ÁÁÁ O ÁÁÁ...

Page 10: ...t high voltage X1 CLK 0 8VCC 2 4 V VOL Output low voltage IOL 2 4 mA 0 2 0 4 V VOH Output high voltage except OD outputs 4 IOH 400 µA VCC 0 5 V IIX1PD X1 CLK input current power down VIN 0 V to VCC 0 5 0 05 0 5 µA IILX1 X1 CLK input low current operating VIN 0 V 130 0 µA IIHX1 X1 CLK input high current operating VIN VCC 0 130 µA Input leakage current II All except input port pins VIN 0 V to VCC 0 ...

Page 11: ...output low current in off state VIN 0 V 0 5 µA IODH Open drain output high current in off state VIN VCC 0 5 µA Power supply current6 ICC Operating mode CMOS input levels 5 mA Power down mode CMOS input levels 1 5 0 mA NOTES 1 Parameters are valid over specified temperature and voltage range 2 All voltage measurements are referenced to ground GND For testing all inputs swing between 0 4 V and 3 0 V...

Page 13: ...referenced at input voltages of 0 8 V and 2 0 V and output voltages of 0 8 V and 2 0 V as appropriate 3 Test conditions for outputs CL 125 pF except open drain outputs Test conditions for open drain outputs CL 125 pF constant current source 2 6 mA 4 Typical values are the average values at 25 C and 5 V 5 Timing is illustrated and referenced to the WRN and RDN Inputs Also CEN may be the strobing in...

Page 15: ...surements are referenced to ground GND For testing all inputs swing between 0 4 V and 3 0 V with a transition time of 5 ns maximum For X1 CLK this swing is between 0 4 V and 0 8 VCC All time measurements are referenced at input voltages of 0 8 V and 2 0 V and output voltages of 0 8 V and 2 0 V as appropriate 3 Test conditions for outputs CL 125 pF except open drain outputs Test conditions for open...

Page 16: ...consists of a crystal oscillator a baud rate generator a programmable 16 bit counter timer and four clock selectors The crystal oscillator operates directly from a crystal connected across the X1 CLK and X2 inputs If an external clock of the appropriate frequency is available it may be connected to X1 CLK The clock serves as the basic timing reference for the Baud Rate Generator BRG the counter ti...

Page 17: ...estarts the C T the receipt of a character after the C T has timed out will clear the counter ready bit ISR 3 and the interrupt Invoking the Set Timeout Mode On command CRx 0xAn will also clear the counter ready bit and stop the counter until the next character is received The counter timer is controlled with six commands Start Stop C T Read Write Counter Timer lower register and Read Write Counte...

Page 18: ...CR register The break is terminated by a STOP BREAK command or a transmitter reset If CTS option is enabled MR2 4 1 the CTS input at IP0 or IP1 must be Low in order for the character to be transmitted The transmitter will check the state of the CTS input at the beginning of the character transmitted If it is found to be High the transmitter will delay the transmission of any following characters u...

Page 19: ... situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt This counter times out after 64 bit times It is reset each time a character is transferred from the receiver shift register to the RxFIFO or a read of the RxFIFO is executed Receiver Time out Mode In addition to the watch dog timer described in the receiver section the c...

Page 20: ...ally whether or not the receiver is enabled PROGRAMMING The operation of the UART is programmed by writing control words into the appropriate registers Operational feedback is provided via status registers which can be read by the CPU The addressing of the registers is described in Table 1 The contents of certain control registers are initialized to zero on RESET Care should be exercised if the co...

Page 21: ...th CSR 1 Receiver Clock Select Code Transmitter Clock select code SR 1 Received Break Framing Error Parity Error Overrun Error TxEMT TxRDY RxFULL RxRDY CR 2 Channel Command codes Disable Tx Enable Tx Disable Rx Enable Rx RxFIFO 3 Read 8 bits from Rx FIFO TxFIFO 3 Write 8 bits to Tx FIFO IPCR 4 Delta IP3 Delta IP2 Delta IP1 Delta IP0 State of IP3 State of IP2 State of IP1 State of IP0 ACR 4 Baud Gr...

Page 23: ...he FIFO is full This is the beginning of the reception of the ninth byte If the FIFO is not read before the start of the tenth or 17th byte an overrun condition will occur and the tenth or 17th or 17th byte will be lost However the bit in OPR 0 is not reset and RTSN will be asserted again when an empty FIFO position is available This feature can be used for flow control to prevent overrun in the r...

Page 24: ...ed to the receiver input 2 The transmit clock is used for the receiver 3 The TxD output is held High 4 The RxD input is ignored 5 The transmitter must be enabled but the receiver need not be enabled 6 CPU to transmitter and receiver communications continue normally MR2 7 6 11 selects remote loop back diagnostic mode In this mode 1 Received data is reclocked and retransmitted on the TxD out put 2 T...

Page 25: ...until CTSN goes low Changes in CTSN while a character is being transmitted do not affect the transmission of that character MR2 3 0 Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character Stop bit lengths of 9 16 to 1 and 1 9 16 to 2 bits in increments of 1 16 bit can be programmed for character lengths of 6 7 and 8 bits For a character lengths o...

Page 26: ...00 3600 57 6K 57 6K 0110 1 200 1 200 7200 7 200 115 2K 115 2K 0111 1 050 2 000 1 050 2 000 1 050 2 000 1000 2 400 2 400 14 4K 14 4K 57 6K 57 6K 1001 4 800 4 800 28 8K 28 8K 4 800 4 800 1010 7 200 1 800 7 200 1 800 57 6K 14 4K 1011 9 600 9 600 57 6K 57 6K 9 600 9 600 1100 38 4K 19 2K 230 4K 115 2K 38 4K 19 2K 1101 Timer Timer Timer Timer Timer Timer 1110 IP4 16X IP4 16X IP4 16X IP4 16X IP4 16X IP4 ...

Page 27: ...The transmitter must be enabled for this command to be accepted 0111 Stop break The TxD line will go High marking within two bit times TxD will remain High for one bit time be fore the next character if any is transmitted 1000 Assert RTSN Causes the RTSN output to be asserted Low 1001 Negate RTSN Causes the RTSN output to be negated High 1010 Set Timeout Mode On The receiver in this channel will r...

Page 28: ...rror bit stores the receive A D Address Data bit SR 4 Overrun Error This bit when set indicates that one or more characters in the received data stream have been lost It is set upon receipt of a new character when the FIFO is full and a character is already in the receive shift register waiting for an empty FIFO position When this occurs the character in the receive shift register and its break de...

Page 29: ...e it goes Low The output returns to the High state when the counter is stopped by a stop counter command Note that this output is not masked by the contents of the IMR 10 Reserved 11 Reserved OPCR 1 0 OP2 Output Select This field programs the OP2 output to provide one of the following 00 The complement of OPR 2 01 The 16X clock for the transmitter This is the clock selected by CSR 3 0 and will be ...

Page 30: ...ter IPCR cause the input change bit in the interrupt status register ISR 7 to be set If a bit is in the on state the setting of the corresponding bit in the IPCR will also result in the setting of ISR 7 which results in the generation of an interrupt output if IMR 7 1 If a bit is in the off state the setting of that bit in the IPCR has no effect on ISR 7 Table 7 ACR 6 4 field definition ACR 6 4 MO...

Page 31: ...received break It is reset when the CPU issues a reset break change interrupt command ISR 1 Rx Interrupt This bit indicates that the receiver is interrupting according to the fill level programmed by the MR0 and MR1 registers This bit has a different meaning than the receiver ready full bit in the status register ISR 0 Tx Interrupt This bit indicates that the transmitter is interrupting according ...

Page 32: ...lues are preserved and used for the next count cycle In the counter mode the current value of the upper and lower 8 bits of the counter CTU CTL may be read by the CPU It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read However n...

Page 33: ...TN tRES SD00696 RESETN tRES 80XXX Mode 68XXX Mode Figure 4 Reset Timing A0 A3 CEN tAS tCS tCH RDN tRW tRWD D0 D7 READ tDD tDF FLOAT FLOAT VALID NOT VALID WDN tRWD VALID D0 D7 WRITE tDS tDH tAH SD00087 NOTE Bus action in the 80XXX mode terminates on the rise of CEN WRN or RDN which ever one occurs first Figure 5 Bus Timing 80XXX mode ...

Page 34: ...N is low SD00687 Figure 6 Bus Timing Read Cycle 68XXX mode X1 CLK A1 A4 RWN CSN D0 D7 DTACKN tCSC tAS tCS tDH tDAT tDAH tCH tRWD tDS tDCW tAH NOTE DACKN low requires two rising edges of X1 clock after CSN is low SD00688 Figure 7 Bus Timing Write Cycle 68XXX mode NOTE For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers ...

Page 35: ...2004 Oct 21 35 X1 CLK INTRN IACKN D0 D7 DTACKN tCSC tDD tDF tCSD tDAL tDCR tDAH tDAT NOTE DACKN low requires two rising edges of X1 clock after CSN is low SD00149 Figure 8 Interrupt Cycle Timing 68XXX mode b OUTPUT PINS RDN IP0 IP6 WRN OP0 OP7 tPS tPH tPD OLD DATA NEW DATA a INPUT PINS SD00135 Figure 9 Port Timing ...

Page 36: ...t are pronounced and can greatly affect the resultant measurement VM VOL 0 5V VOL WRN INTERRUPT1 OUTPUT tIR VM VOL 0 5V VOL RDN INTERRUPT1 OUTPUT tIR SD00136 Figure 10 Interrupt Timing 80xxx mode C1 C2 24pF FOR CL 20pF tCLK tCTC tRx tTx X1 CLK CTCLK RxC TxC tCLK tCTC tRx tTx VCC 470Ω X1 X2 CLK NOTE X2 MUST BE LEFT OPEN X2 3 6864MHz X1 C1 C2 SC28L91 NOTE RESISTOR REQUIRED FOR TTL INPUT TO UART CIRC...

Page 37: ...TPUT SD00138 Figure 12 Transmitter External Clocks tRXS tRXH RxC 1X INPUT RxD SD00139 Figure 13 Receiver External Clock TRANSMITTER ENABLED TxD D1 D2 D3 D4 D6 BREAK TxRDY SR2 WRN D1 D8 D9 D10 D12 START BREAK STOP BREAK D11 WILL NOT BE WRITTEN TO THE TxFIFO CTSN1 IP0 RTSN2 OP0 OPR 0 1 OPR 0 1 NOTES 1 Timing shown for MR2 4 1 2 Timing shown for MR2 5 1 SD00155 Figure 14 Transmitter Timing ...

Page 38: ...ATA D10 D11 WILL BE LOST DUE TO OVERRUN OVERRUN SR4 RESET BY COMMAND RTS1 OP0 OPR 0 1 NOTES 1 Timing shown for MR1 7 1 2 Shown for OPCR 4 1 and MR 6 0 SD00156 Figure 15 Receiver Timing TRANSMITTER ENABLED TxD ADD 1 TxRDY SR2 WRN MR1 4 3 11 MR1 2 1 1 BIT 9 D0 0 BIT 9 ADD 2 1 BIT 9 MASTER STATION ADD 1 MR1 2 0 D0 MR1 2 1 ADD 2 RxD ADD 1 1 BIT 9 D0 0 BIT 9 ADD 2 1 BIT 9 PERIPHERAL STATION 0 BIT 9 0 B...

Page 39: ...V or 5 0 V Universal Asynchronous Receiver Transmitter UART 2004 Oct 21 39 INTRN DACKN D0 D7 TxDA B OP0 OP7 125pF 5V I 2 4mA 125pF I 2 4mA VOL return to VCC for a 0 level I 400µA VOH return to VSS for a 1 level SD00690 Figure 17 Test Conditions on Outputs ...

Page 40: ...Philips Semiconductors Product data sheet SC28L91 3 3 V or 5 0 V Universal Asynchronous Receiver Transmitter UART 2004 Oct 21 40 PLCC44 plastic leaded chip carrier 44 leads SOT187 2 ...

Page 41: ...emiconductors Product data sheet SC28L91 3 3 V or 5 0 V Universal Asynchronous Receiver Transmitter UART 2004 Oct 21 41 QFP44 plastic quad flat package 44 leads lead length 1 3 mm body 10 x 10 x 1 75 mm SOT307 2 ...

Page 42: ...DCW max changed from 20 ns to 35 ns tCSC min changed from 10 ns to 16 ns AC electrical characteristics 3 3 V table tAH min changed from 25 ns to 33 ns tDS min changed from 25 ns to 43 ns tRWD min changed from 20 ns to 27 ns tPD max changed from 70 ns to 75 ns tIRH max changed from 60 ns to 79 ns tCLK min changed from 30 ns to 35 ns tTXD max changed from 60 ns to 78 ns tDCR max changed from 25 ns t...

Page 43: ...ct ProcessChangeNotification CPCN PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information For additional i...

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