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Philips SC16C2550, Manual

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Philips SC16C2550 Manual Download Page 30

Philips Semiconductors

SC16C2550

Dual UART with 16 bytes of transmit and receive FIFOs and IrDA

encoder/decoder

Product data

Rev. 03 — 19 June 2003

30 of 46

9397 750 11621

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

9.

Static characteristics

[1]

Except x

2

, V

OL

= 1 V typical.

Table 25:

DC electrical characteristics

T

amb

=

−

40

°

C to +85

°

C; V

CC

= 2.5 V, 3.3 V or 5.0 V

±

10%, unless otherwise specified.

Symbol

Parameter

Conditions

2.5 V

3.3 V

5.0 V

Unit

Min

Max

Min

Max

Min

Max

V

IL(CK)

LOW-level clock input voltage

−

0.3

0.45

−

0.3

0.6

−

0.5

0.6

V

V

IH(CK)

HIGH-level clock input voltage

1.8

V

CC

2.4

V

CC

3.0

V

CC

V

V

IL

LOW-level input voltage
(except X1 clock)

−

0.3

0.65

−

0.3

0.8

−

0.5

0.8

V

V

IH

HIGH-level input voltage
(except X1 clock)

1.6

-

2.0

-

2.2

-

V

V

OL

LOW-level output voltage
on all outputs

[1]

I

OL

= 5 mA

(databus)

-

-

-

-

-

0.4

V

I

OL

= 4 mA

(other outputs)

-

-

-

0.4

-

-

V

I

OL

= 2 mA

(databus)

-

0.4

-

-

-

-

V

I

OL

= 1.6 mA

(other outputs)

-

0.4

-

-

-

-

V

V

OH

HIGH-level output voltage

I

OH

=

−

5 mA

(databus)

-

-

-

-

2.4

-

V

I

OH

=

−

1 mA

(other outputs)

-

-

2.0

-

-

-

V

I

OH

=

−

800

µ

A

(data bus)

1.85

-

-

-

-

-

V

I

OH

=

−

400

µ

A

(other outputs)

1.85

-

-

-

-

-

V

I

LIL

LOW-level input leakage
current

-

±

10

-

±

10

-

±

10

µ

A

I

CL

clock leakage

-

±

30

-

±

30

-

±

30

µ

A

I

CC

supply current

f = 5 MHz

-

3.5

-

4.5

-

4.5

mA

C

i

input capacitance

-

5

-

5

-

5

pF

Summary of Contents for SC16C2550

Page 1: ...equirements An internal loop back capability allows on board diagnostics Independent programmable baud rate generators are provided to select transmit and receive baud rates The SC16C2550 operates at 5 V 3 3 V and 2 5 V and the Industrial temperature range and is available in plastic PLCC44 LQFP48 and DIP40 packages 2 Features 2 channel UART 5 V 3 3 V and 2 5 V operation Industrial temperature ran...

Page 2: ...abilities 3 State output TTL drive capabilities for bi directional data bus and control bus Line Break generation and detection Internal diagnostic capabilities Loop back controls for communications link fault isolation Prioritized interrupt system controls Modem control functions CTS RTS DSR DTR RI DCD 3 Ordering information Table 1 Ordering information Type number Package Name Description Versio...

Page 3: ...50 block diagram TRANSMIT FIFO REGISTER TXA TXB RECEIVE SHIFT REGISTER RECEIVE FIFO REGISTER RXA RXB INTERCONNECT BUS LINES AND CONTROL SIGNALS SC16C2550 TRANSMIT SHIFT REGISTER MODEM CONTROL LOGIC DTRA DTRB RTSA RTSB OP2A OP2B CLOCK AND BAUD RATE GENERATOR CTSA CTSB RIA RIB CDA CDB DSRA DSRB XTAL2 XTAL1 DATA BUS AND CONTROL LOGIC D0 D7 IOR IOW RESET A0 A2 CSA CSB REGISTER SELECT LOGIC INTA INTB T...

Page 4: ...ics N V 2003 All rights reserved 5 Pinning information 5 1 Pinning Fig 2 DIP40 pin configuration SC16C2550IN40 002aaa105 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D0 D1 D2 D3 D4 D5 D6 D7 RXB RXA TXA TXB OP2B CSA CSB XTAL1 XTAL2 IOW CDB GND VCC RIA CDA DSRA CTSA RESET DTRB DTRA RTSA OP2A INTA INTB A0 A1 A2 CTSB RTSB RIB DSRB IOR 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 ...

Page 5: ...N V 2003 All rights reserved Fig 3 PLCC44 pin configuration SC16C2550IA44 002aaa103 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 D4 D3 D2 D1 D0 TXRDYA V CC RIA CDA DSRA CTSA XTAL1 XTAL2 IOW CDB GND RXRDYB IOR DSRB RIB RTSB CTSB D5 D6 D7 RXB RXA TXRDYB TXA TXB OP2B CSA CSB RESET DTRB DTRA RTSA OP2A RXRDYA INTA INTB A0 A1 ...

Page 6: ...ion Symbol Pin Type Description DIP40 PLCC44 LQFP48 A0 28 31 28 I Address 0 select bit Internal register address selection A1 27 30 27 I Address 1 select bit Internal register address selection A2 26 29 26 I Address 2 select bit Internal register address selection CSA CSB 14 15 16 17 10 11 I Chip Select A B Active LOW This function is associated with individual channels A through B These pins enab...

Page 7: ...he UART transmitter output and the receiver input will be disabled during reset time See Section 7 11 SC16C2550 external reset condition for initialization details RXRDYA RXRDYB 34 23 31 18 O Receive Ready A B Active LOW This function is associated with PLCC44 and LQFP48 packages only This function provides the RX FIFO RHR status for individual receive channels A B RXRDYn is primarily intended for...

Page 8: ...n be controlled via the modem control register Writing a logic 1 to MCR 0 will set the DTR output to logic 0 enabling the modem This pin will be a logic 1 after writing a logic 0 to MCR 0 or after a reset This pin has no effect on the UART s transmit or receive operation RIA RIB 39 23 43 26 41 21 I Ring Indicator Active LOW These inputs are associated with individual UART channels A through B A lo...

Page 9: ... within a given time For example the ST16C2450 without a receive FIFO will require unloading of the RHR in 93 microseconds this example uses a character length of 11 bits including start stop bits at 115 2 kbits s This means the external CPU will have to service the receive FIFO less than every 100 microseconds However with the 16 byte FIFO in the SC16C2550 the data buffer will not require unloadi...

Page 10: ...c 0 2 These registers are accessible only when LCR 7 is a logic 1 3 Enhanced Feature Register Xon1 2 and Xoff1 2 are accessible only when the LCR is set to BF HEX Table 3 Serial port selection Chip Select Function CSA CSB 1 none CSA 0 UART channel A CSB 0 UART channel B Table 4 Internal registers decoding A2 A1 A0 READ mode WRITE mode General register set THR RHR IER ISR MCR MSR FCR LSR SPR 1 0 0 ...

Page 11: ...aches the programmed trigger level The RTS pin will not be forced to a logic 1 RTS off until the receive FIFO reaches the next trigger level However the RTS pin will return to a logic 0 after the data buffer FIFO is unloaded to the next trigger level below the programmed trigger However under the above described conditions the SC16C2550 will continue to accept data until the receive FIFO is full 6...

Page 12: ...h eight bits of character information the actual number of bits is dependent on the programmed word length Line Control Register bits LCR 0 1 define the number of character bits i e either 5 bits 6 bits 7 bits or 8 bits The word length selected by LCR 0 1 also determine the number of bits that will be used for the special character comparison Bit 0 in the X registers corresponds with the LSB bit f...

Page 13: ...maximum data rate it is necessary to use full rail swing on the clock input The SC16C2550 can be configured for internal or external clock operation For internal clock oscillator operation an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins Alternatively an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator fo...

Page 14: ... back capability allows on board diagnostics In the loop back mode the normal modem interface pins are disconnected and reconfigured for loop back internally see Figure 6 MCR 0 3 register bits are used for controlling loop back diagnostic testing In the loop back mode the transmitter output TX and the receiver input RX are disconnected from their associated interface pins and instead are connected...

Page 15: ...rcuits In this mode the receiver and transmitter interrupts are fully operational The Modem Control Interrupts are also operational Fig 6 Internal loop back mode diagram TRANSMIT FIFO REGISTER TXA TXB RECEIVE SHIFT REGISTER RECEIVE FIFO REGISTER RXA RXB INTERCONNECT BUS LINES AND CONTROL SIGNALS SC16C2550 TRANSMIT SHIFT REGISTER MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL2 XTAL1 DATA BU...

Page 16: ...rrupt receive holding register 0 1 0 FCR 00 RCVR trigger MSB RCVR trigger LSB reserved 0 reserved 0 DMA mode select XMIT FIFO reset RCVR FIFO reset FIFOs enable 0 1 0 ISR 01 FIFOs enabled FIFOs enabled INT priority bit 4 INT priority bit 3 INT priority bit 2 INT priority bit 1 INT priority bit 0 INT status 0 1 1 LCR 00 divisor latch enable set break set parity even parity parity enable stop bits w...

Page 17: ...ed to the center of the start bit At this time the start bit is sampled and if it is still a logic 0 it is validated Evaluating the start bit in this manner prevents the receiver from assembling a false character Receiver status codes will be posted in the LSR 7 2 Interrupt Enable Register IER The Interrupt Enable Register IER masks the interrupts from receiver ready transmitter empty line status ...

Page 18: ...nsmit FIFO is empty due to the unloading of the data by the TSR and UART for transmission via the transmission media The interrupt is cleared either by reading the ISR register or by loading the THR with new data characters 2 IER 2 Receive Line Status interrupt This interrupt will be issued whenever a receive data error condition exists as reflected in LSR 1 4 Logic 0 Disable the receiver line sta...

Page 19: ...y LSR 7 will show if any FIFO data errors occurred 7 3 FIFO Control Register FCR This register is used to enable the FIFOs clear the FIFOs set the receive FIFO trigger levels and select the DMA mode 7 3 1 DMA mode Mode 0 FCR bit 3 0 Set and enable the interrupt for each single transmit or receive operation and is similar to the 16C450 mode Transmit Ready TXRDY on PLCC44 and LQFP48 packages will go...

Page 20: ...gic 0 Once active the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register Receive operation in mode 0 When the SC16C2550 is in mode 0 FCR 0 logic 0 or in the FIFO mode FCR 3 logic 0 and there is at lease one character in the receive FIFO the RXRDY pin will be a logic 0 Once active the RXRDY pin on PLCC44 and LQFP48 packages will go to a logic 1 whe...

Page 21: ...hese interrupt levels 1 FCR 1 RCVR FIFO reset Logic 0 Receive FIFO not reset normal default condition Logic 1 Clears the contents of the receive FIFO and resets the FIFO counter logic the receive shift register is not cleared or altered This bit will return to a logic 0 after clearing the FIFO 0 FCR 0 FIFOs enabled Logic 0 Disable the transmit and receive FIFO normal default condition Logic 1 Enab...

Page 22: ...These bits indicate the source for a pending interrupt at interrupt priority levels 1 2 and 3 see Table 11 Logic 0 or cleared default condition 0 ISR 0 INT status Logic 0 An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine Logic 1 No interrupt pending normal default condition Table 13 Line Control Register bits description Bit Symbol D...

Page 23: ... Electronics N V 2003 All rights reserved Table 14 LCR 5 3 parity selection LCR 5 LCR 4 LCR 3 Parity selection X X 0 no parity X 0 1 ODD parity 0 1 1 EVEN parity 0 0 1 forced parity 1 1 1 1 forced parity 0 Table 15 LCR 2 stop bit length LCR 2 Word length Stop bit length bit times 0 5 6 7 8 1 1 5 1 1 2 1 6 7 8 2 Table 16 LCR 1 0 word length LCR 1 LCR 0 Word length 0 0 5 0 1 6 1 0 7 1 1 8 ...

Page 24: ...and the receiver input RX CTS DSR CD and RI are disconnected from the SC16C2550 I O pins Internally the modem data and control pins are connected into a loop back data configuration see Figure 6 In this mode the receiver and transmitter interrupts remain fully operational The Modem Control Interrupts are also operational but the interrupts sources are switched to the lower four bits of the Modem C...

Page 25: ... Register Empty indicator This bit indicates that the UART is ready to accept a new character for transmission In addition this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register The bit is reset to a logic 0 concurrently with the...

Page 26: ...or 0 LSR 0 Receive data ready Logic 0 No data in receive holding register or FIFO normal default condition Logic 1 Data has been received and is saved in the receive holding register or FIFO Table 18 Line Status Register bits description continued Bit Symbol Description Table 19 Modem Status Register bits description Bit Symbol Description 7 MSR 7 CD During normal operation this bit is the complem...

Page 27: ...n Logic 1 The CTS input to the SC16C2550 has changed state since the last time it was read A modem Status Interrupt will be generated Table 19 Modem Status Register bits description continued Bit Symbol Description Table 20 Enhanced Feature Register bits description Bit Symbol Description 7 EFR 7 Automatic CTS flow control Logic 0 Automatic CTS flow control is disabled normal default condition Log...

Page 28: ...om altering or overwriting the SC16C2550 enhanced functions Logic 0 disable latch enhanced features IER 7 4 ISR 5 4 FCR 5 4 and MCR 7 5 are saved to retain the user settings then IER 7 4 ISR 5 4 FCR 5 4 and MCR 7 5 are set to a logic 0 to be compatible with SC16C554 mode Normal default condition Logic 1 Enables the enhanced functions When this bit is set to a logic 1 all enhanced features of the S...

Page 29: ... LCR 7 0 0 MCR MCR 7 0 0 LSR LSR 7 0 LSR 6 5 1 LSR 4 0 0 MSR MSR 7 4 input signals MSR 3 0 0 SPR SFR 7 0 1 DLL DLL 7 0 X DLM DLM 7 0 X Table 23 Reset state for outputs Output Reset state TXA TXB Logic 1 OP2A OP2B Logic 1 RTSA RTSB Logic 1 DTRA DTRB Logic 1 INTA INTB 3 State condition Table 24 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Condition...

Page 30: ...l clock input voltage 0 3 0 45 0 3 0 6 0 5 0 6 V VIH CK HIGH level clock input voltage 1 8 VCC 2 4 VCC 3 0 VCC V VIL LOW level input voltage except X1 clock 0 3 0 65 0 3 0 8 0 5 0 8 V VIH HIGH level input voltage except X1 clock 1 6 2 0 2 2 V VOL LOW level output voltage on all outputs 1 IOL 5 mA databus 0 4 V IOL 4 mA other outputs 0 4 V IOL 2 mA databus 0 4 V IOL 1 6 mA other outputs 0 4 V VOH H...

Page 31: ...elect hold time from IOR 0 0 0 ns t9d read cycle delay 25 pF load 20 20 20 ns t12d delay from IOR to data 25 pF load 77 26 23 ns t12h data disable time 25 pF load 15 15 15 ns t13d IOW delay from chip select 10 10 10 ns t13w IOW strobe width 20 2 20 2 15 2 ns t13h chip select hold time from IOW 0 0 0 ns t15d write cycle delay 3 25 25 20 ns t16s data set up time 20 20 15 ns t16h data hold time 15 5 ...

Page 32: ... 46 9397 750 11621 Koninklijke Philips Electronics N V 2003 All rights reserved 10 1 Timing diagrams Fig 7 General write timing DATA ACTIVE ACTIVE VALID ADDRESS 002aaa109 t6s t13h t13d t13w t15d t16s t16h A0 A2 CSx IOW D0 D7 t6h Fig 8 General read timing DATA ACTIVE ACTIVE VALID ADDRESS 002aaa110 t6s t7h t7d t7w t9d t12d t12h A0 A2 CSx IOR D0 D7 t6h ...

Page 33: ... 11621 Koninklijke Philips Electronics N V 2003 All rights reserved Fig 9 Modem input output timing t17d ACTIVE IOW CHANGE OF STATE CHANGE OF STATE RTS DTR DCD CTS DSR CHANGE OF STATE CHANGE OF STATE CHANGE OF STATE ACTIVE ACTIVE ACTIVE t18d t18d INT ACTIVE ACTIVE ACTIVE IOR RI t19d 002aaa111 t18d Fig 10 External clock timing t2w EXTERNAL CLOCK 002aaa112 t1w t3w ...

Page 34: ... data Rev 03 19 June 2003 34 of 46 9397 750 11621 Koninklijke Philips Electronics N V 2003 All rights reserved Fig 11 Receive timing D0 D1 D2 D3 D4 D5 D6 D7 ACTIVE ACTIVE 16 BAUD RATE CLOCK 002aaa113 t21d NEXT DATA START BIT STOP BIT PARITY BIT START BIT t20d RX INT IOR DATA BITS 5 8 5 DATA BITS 6 DATA BITS 7 DATA BITS ...

Page 35: ...rights reserved Fig 12 Receive ready timing in non FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 ACTIVE DATA READY ACTIVE 002aaa114 t26d NEXT DATA START BIT STOP BIT PARITY BIT START BIT t25d RX RXRDY IOR DATA BITS 5 8 Fig 13 Receive ready timing in FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 ACTIVE DATA READY ACTIVE 002aaa115 t26d STOP BIT PARITY BIT START BIT t25d RX RXRDY IOR DATA BITS 5 8 FIRST BYTE THAT REACHES TH...

Page 36: ...3 19 June 2003 36 of 46 9397 750 11621 Koninklijke Philips Electronics N V 2003 All rights reserved Fig 14 Transmit timing D0 D1 D2 D3 D4 D5 D6 D7 ACTIVE TX READY ACTIVE 16 BAUD RATE CLOCK 002aaa116 t24d NEXT DATA START BIT STOP BIT PARITY BIT START BIT t22d TX INT IOW DATA BITS 5 8 5 DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE t23d ...

Page 37: ... 03 19 June 2003 37 of 46 9397 750 11621 Koninklijke Philips Electronics N V 2003 All rights reserved Fig 15 Transmit ready timing in non FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 TRANSMITTER NOT READY 002aaa117 NEXT DATA START BIT STOP BIT PARITY BIT START BIT t27d TX TXRDY IOW DATA BITS 5 8 ACTIVE D0 D7 BYTE 1 ACTIVE TRANSMITTER READY ...

Page 38: ... Rev 03 19 June 2003 38 of 46 9397 750 11621 Koninklijke Philips Electronics N V 2003 All rights reserved Fig 16 Transmit ready timing in FIFO mode DMA mode 1 D0 D1 D2 D3 D4 D5 D6 D7 FIFO FULL 002aaa118 STOP BIT PARITY BIT START BIT t27d TX TXRDY IOW DATA BITS 5 8 ACTIVE D0 D7 BYTE 16 5 DATA BITS 6 DATA BITS 7 DATA BITS t28d ...

Page 39: ...imensions are derived from the original mm dimensions SOT129 1 99 12 27 03 02 13 A min A max b Z max w ME e1 1 70 1 14 0 53 0 38 0 36 0 23 52 5 51 5 14 1 13 7 3 60 3 05 0 254 2 54 15 24 15 80 15 24 17 42 15 90 2 25 4 7 0 51 4 0 067 0 045 0 021 0 015 0 014 0 009 2 067 2 028 0 56 0 54 0 14 0 12 0 01 0 1 0 6 0 62 0 60 0 69 0 63 0 089 0 19 0 02 0 16 051G08 MO 015 SC 511 40 MH c e 1 ME A L seating plan...

Page 40: ...ons are derived from the original inch dimensions Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included SOT187 2 D 1 E 1 16 66 16 51 HD HE 17 65 17 40 ZD 1 max ZE 1 max 2 16 b1 0 81 0 66 k 1 22 1 07 0 180 0 165 0 02 0 12 A3 0 25 0 01 0 656 0 650 0 05 0 695 0 685 0 085 0 007 0 004 0 007 Lp 1 44 1 02 0 057 0 040 0 656 0 650 0 695 0 685 eD eE 16 00 14 99 0 63 0 59...

Page 41: ...UE DATE IEC JEDEC JEITA mm 1 6 0 20 0 05 1 45 1 35 0 25 0 27 0 17 0 18 0 12 7 1 6 9 0 5 9 15 8 85 0 95 0 55 7 0 o o 0 12 0 1 0 2 1 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included 0 75 0 45 SOT313 2 MS 026 136E05 00 01 19 03 02 25 D 1 1 1 7 1 6 9 HD 9 15 8 85 E Z 0 95 0 55 D bp e E B 12 D H bp E H v M B D ZD A ZE e v M A 1 4...

Page 42: ...s The device may be mounted up to the seating plane but the temperature of the plastic body must not exceed the specified maximum storage temperature Tstg max If the printed circuit board has been pre heated forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit 12 2 2 Manual soldering Apply the soldering iron 24 V or less to the lead s of ...

Page 43: ... to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end For packages with leads on four sides the footprint must be placed at a 45 ang...

Page 44: ...t penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 6 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 7 Wave soldering is suitable for LQFP Q...

Page 45: ...modification 16 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any dam...

Page 46: ...e flow control 12 6 7 Hardware software and time out interrupts 12 6 8 Programmable baud rate generator 13 6 9 DMA operation 14 6 10 Loop back mode 14 7 Register descriptions 16 7 1 Transmit THR and Receive RHR Holding Registers 17 7 2 Interrupt Enable Register IER 17 7 2 1 IER versus Transmit Receive FIFO interrupt mode operation 18 7 2 2 IER versus Receive Transmit FIFO polled mode operation 19 ...

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