74
7.
Circuit Diagrams and PWB Layouts
SSB: FPGA 1080P: I/O Banks
VCCA_PLL
VCCD_PLL
GNDA_PLL
GND
GND
GND
VCCIO4
VCCINT
1
2
1
2
2
1
GND_PLL2
GND_PLL1
VCCIO
3
VCCIO2
VCCIO1
CLK
M
S
EL
6
5
4
3
2
1
0
7
DATA0
DCLK
TDI
TDO
TM
S
TCK
1
0
CONF_DONE
CONFIG
S
TATU
S
CE
NC
NC
IF7
8
C1
3
IF
8
1 E12
11
12
7F90-
3
D
8
7F90-4 B12
7F90-5 D12
7F90-6 D
3
3
F76 B4
2
3
4
5
F
G
H
IF
8
2 E12
IF
83
E12
1
3
6
7
8
9
10
3
F77 B2
3
F7
8
C2
3
F79 B2
3
F9
3
C6
F
IF76 C1
3
6
7
8
E
9F91 C4
9F92 C1
3
9F9
3
E14
9
10
2
3
4
5
B
C
D
IF7
3
C9
IF74 E9
IF75 E9
IF91 B2
E
3
F75 B2
14
1
G
H
A
FPGA 10
8
0p: I/O BANK
S
7F90-7 G12
9F90 B2
14
9F95 C5
9F94 C5
3
F94 C6
3
F95 C9
3
F9
8
C9
7F90-1 B
3
7F90-2 B
8
11
1
3
12
FF94 C7
1
C
A
IF
8
5 F1
3
IF
8
4 F1
3
IF92 C2
IF9
3
C7
IF94 B9
9F96 B11
9F97 C11
IF95 B9
IF96 B2
FF9
3
C7
FF91 C9
FF92 C9
FF90 B4
9F9
8
C11
IF
8
9 C4
IF
8
6 F12
IF
8
7 G12
IF
88
G12
IF90 B2
B
D
+
3
V
3
-FPGA
3
F9
8
47R
IF95
3
F76
10K
9F97
FF91
RE
S
P7
T15
T2
FF9
3
C10
C7
E10
E7
B16
G14
K14
R16
M10
M7
P10
F11
G9
H10
H7
J7
B1
G
3
K
3
R1
A15
A2
G
8
M6
E11
L5
N5
D12
F12
M5
E12
L6
R15
R2
T1
T16
B15
B2
C
8
C9
E
8
E9
H9
J14
J
3
J
8
J9
K9
M
8
A16
M9
P
8
P9
Φ
POWER
A1
H14
H
3
H
8
EP2C5F256C7N
7F90-6
FF94
IO_T4|LVD
S
56p
T4
IO_T5|LVD
S
55p
T5
IO_T6
T6
IO_T7|LVD
S
54p
T7
IO_T
8
|LVD
S
5
3
p
T
8
IO_T9|LVD
S
52p
T9
IO_R
8
|LVD
S
5
3
n
R
8
IO_R9|LVD
S
52n
R9
IO_T10|LVD
S
49n
T10
IO_T11|LVD
S
51p
T11
IO_T12|LVD
S
46p
T12
IO_T1
3
|LVD
S
45p
T1
3
IO_T14|LVD
S
44p
T14
IO_T
3
|LVD
S
5
8
p
T
3
IO_R11|LVD
S
51n
R11
IO_R12|LVD
S
46n
R12
IO_R1
3
|LVD
S
45n
R1
3
IO_R14|LVD
S
44n
R14
IO_R
3
|LVD
S
5
8
n
R
3
IO_R4|LVD
S
56n
R4
IO_R5|LVD
S
55n
R5
IO_R7|LVD
S
54n
R7
IO_N
8
|VREFB4N1
N
8
IO_N9|LVD
S
59p
N9
IO_P11
P11
IO_P12|LVD
S
47p
P12
IO_P1
3
|LVD
S
47n
P1
3
IO_P4|LVD
S
57n
P4
IO_P5|LVD
S
57p
P5
IO_R10|LVD
S
49p
R10
IO_L11|LVD
S
4
3
n
L11
IO_L12
L12
IO_L7|LVD
S
60p
L7
IO_L
8
|LVD
S
60n
L
8
IO_L9|LVD
S
50p
L9
IO_M11|LVD
S
4
3
p
M11
IO_N10|LVD
S
59n
N10
IO_N11|VREFB4N0
N11
7F90-5
EP2C5F256C7N
IO_K10|LVD
S
4
8
n
K10
IO_K11|LVD
S
4
8
p
K11
IO_L10|LVD
S
50n
L10
IF
8
9
BANK4
Φ
+1V2-PLL
+1V2-FPGA
IF94
IF
88
+1V2-FPGA
9F94
9F9
3
+
3
V
3
3
F94
100R
IF7
3
IF
8
7
IO_N14|LVD
S
41p
N14
IO_N15|LVD
S3
9n
N15
IO_N16|LVD
S3
9p
N16
IO_P14
P14
IO_P15|LVD
S
40n
P15
IO_P16|LVD
S
40p
P16
IO_L15|LVD
S3
7n
L15
IO_L16|LVD
S3
7p
L16
IO_M12|LVD
S
42p
M12
IO_M14|VREFB
3
N1
M14
IO_M15|LVD
S38
n
M15
IO_M16|LVD
S38
p
M16
IO_N12|LVD
S
42n
N12
IO_N1
3
|LVD
S
41n
N1
3
IO_H11|LVD
S3
2p
H11
IO_H12|LVD
S3
5n
H12
IO_H1
3
|VREFB
3
N0
H1
3
IO_J11|LVD
S3
2n
J11
IO_J12|LVD
S3
5p
J12
IO_K15|LVD
S3
6p
K15
IO_K16|LVD
S3
6n
K16
IO_L14
L14
E14
IO_E14|PLL2_OUTp
IO_E16
E16
IO_F15|LVD
S33
n
F15
IO_F16|LVD
S33
p
F16
IO_G12|LVD
S3
1n
G12
IO_G1
3
|LVD
S3
1p
G1
3
IO_G15|LVD
S3
4p
G15
IO_G16|LVD
S3
4n
G16
IO_C14|LVD
S
29n
C14
IO_D1
3
|LVD
S
29p
D1
3
IO_D14|PLL2_OUTn
D14
IO_D15|LVD
S3
0n
D15
IO_D16|LVD
S3
0p
D16
+Vin-FPGA
BANK
3
Φ
7F90-4
EP2C5F256C7N
IF74
+2V5o
u
t-FPGA
+1V2-FPGA
+1V2-FPGA
+1V2-PLL
F1
H4
J1
3
K12
M1
3
F2
H5
G2
G1
G5
H2
H1
J2
J1
H16
H15
J15
J16
J5
L1
3
CONTROL
Φ
7F90-1
EP2C5F256C7N
IF
83
IF
8
2
FF92
3
F77
1K0
RE
S
9F95
RE
S
IF75
+
3
V
3
-FPGA
3
F95
47R
+
3
V
3
-FPGA
47R
3
F75
IF
8
1
IF92
9F90
IF76
IF90
+1V2-FPGA
+1V2-PLL
M4
IO_M4|PLL1_OUTn
N1
IO_N1|LVD
S
1p
N2
IO_N2|LVD
S
1n
P1
IO_P1|LVD
S
0p
P2
IO_P2|LVD
S
0n
P
3
IO_P
3
K5
IO_K5|LVD
S3
n
L1
IO_L1|LVD
S
2p
L2
IO_L2|LVD
S
2n
L
3
IO_L
3
L4
IO_L4|PLL1_OUTp
M1
IO_M1
M2
IO_M2
M
3
IO_M
3
E4
IO_E4|LVD
S
7n
E5
IO_E5|LVD
S8
n
F
3
IO_F
3
|VREFB1N0
F4
IO_F4|C
S
O_
J4
IO_J4|VREFB1N1
K1
IO_K1|LVD
S
4n
K2
IO_K2|LVD
S
4p
K4
IO_K4|LVD
S3
p
C2
IO_C2|LVD
S
9n
C
3
IO_C
3
|A
S
DO
D
3
IO_D
3
|LVD
S
6p
D4
IO_D4|LVD
S
6n
D5
IO_D5|LVD
S8
p
IO_E1|LVD
S
5p
E1
IO_E2|LVD
S
5n
E2
E
3
IO_E
3
|LVD
S
7p
7F90-2
EP2C5F256C7N
BANK1
Φ
C1
IO_C1|LVD
S
9p
+
3
V
3
-FPGA
+1V2-FPGA
RE
S
9F92
IF7
8
IF91
IF
8
5
IF
8
4
IF
8
6
P6
R6
C16
D1
D2
D7
D9
E1
3
E15
J10
J6
K1
3
K6
K7
C15
K
8
N
3
N4
N6
N7
B
8
F1
3
F14
F5
G4
H6
NC
Φ
7F90-7
EP2C5F256C7N
IO_G11|LVD
S
24p
G11
IO_G6|LVD
S
11n
G6
IO_G7|LVD
S
11p
G7
IO_D
8
|VREFB2N1
D
8
IO_E6|LVD
S
1
3
p
E6
IO_F10|LVD
S
12n
F10
IO_F6|LVD
S
1
3
n
F6
IO_F7|LVD
S
19n
F7
IO_F
8
|LVD
S
19p
F
8
IO_F9|LVD
S
12p
F9
IO_G10|LVD
S
24n
G10
IO_C12|LVD
S
27p
C12
IO_C1
3
|LVD
S
27n
C1
3
IO_C4|LVD
S
10p
C4
IO_C5|LVD
S
10n
C5
IO_C6|LVD
S
17p
C6
IO_D10|LVD
S
22p
D10
IO_D11|LVD
S
22n
D11
IO_D6|LVD
S
17n
D6
IO_B14|LVD
S
2
8
n
B14
IO_B
3
|LVD
S
14n
B
3
IO_B4|LVD
S
15n
B4
IO_B5|LVD
S
16n
B5
IO_B6|LVD
S
1
8
n
B6
IO_B7|LVD
S
20p
B7
IO_B9|LVD
S
21p
B9
IO_C11|VREFB2N0
C11
IO_A6|LVD
S
1
8
p
A6
IO_A7|LVD
S
20n
A7
IO_A
8
A
8
IO_A9|LVD
S
21n
A9
IO_B10|LVD
S
2
3
n
B10
IO_B11
B11
IO_B12|LVD
S
25n
B12
IO_B1
3
|LVD
S
26n
B1
3
IO_A10|LVD
S
2
3
p
A10
IO_A11
A11
IO_A12|LVD
S
25p
A12
IO_A1
3
|LVD
S
26p
A1
3
IO_A14|LVD
S
2
8
p
A14
IO_A
3
|LVD
S
14p
A
3
IO_A4|LVD
S
15p
A4
IO_A5|LVD
S
16p
A5
BANK2
Φ
7F90-
3
EP2C5F256C7N
47R
3
F79
+1V2-PLL
IF96
1K0
3
F7
8
RE
S
9F91
FF90
IF9
3
RE
S
9F9
8
3
F9
3
100R
+1V2-PLL
+1V2-FPGA
RE
S
9F96
DV-B2_DEBUG-BREAK
DV-B
3
_AUDIO-MUTE
DV-CLK-PLL
DV-CLK-PLL
PCI-CLK-PNX5050_CLK-MOP
M
S
EL1
S
DA-
SS
B
S
CL-
SS
B
DV-B0_UART2-RX
S
DA-AMBI-
3
V
3
S
CL-AMBI-
3
V
3
DV-B1_UART2-TX
S
D1-A6
S
D1-A7
S
D1-A1
S
D1-A10
S
D1-A11
S
D1-A0
MP-LED
3
MP-LED5
S
D1-CA
S
S
D1-DQ
8
S
D1-DQ6
S
D1-DQ5
S
D1-DQ4
S
D1-DQ1
MP-LED4
S
D1-RA
S
S
D1-WE
S
D1-DQ7
S
D1-DQ
3
S
D1-DQ2
CTRL1-FPGA
CTRL
3
-FPGA
MP-LED1
S
D1-A
3
S
D1-A2
CTRL2-FPGA
CTRL4-FPGA
MP-LED2
DV-R4_Y6
DV-R
3
_Y5
DV-R7_Y9
DV-G6_UV
8
DV-G5_UV7
DV-R2_Y4
DV-R1_Y
3
DV-R0_Y2
DV-R6_Y
8
DV-R5_Y7
DV-G0_UV2
DV-G1_UV
3
DV-G2_UV4
DV-G4_UV6
DV-G
3
_UV5
DV-G7_UV9
DV-FF_DE
DV-H
S
DV-V
S
DV-CLK-PLL
DV-B4_UV0
DV-B5_UV1
DV-B6_Y0
DV-B7_Y1
T
TxFPGAoB-
T
T
TxFPGAoD-
TxFPGAeB-
+1V2-FPGA
TxF
T
TxFPGAeA-
TxFPGAoE-
TxFPGAoCLK-
TxFPGAoC-
TxFPGAoA-
TxFPGAeE-
TxFPGAeD-
TxFPGAeCLK-
TxFPGAeC-
T
S
D1-DQ10
S
D1-A5
S
D1-DQ9
S
D1-C
S
S
D1-A4
T
TxF
T
T
T
T
S
D1-CKE
S
D1-DQ1
3
S
D1-DQ14
S
D1-A9
S
D1-CLK
S
D1-DQ11
S
D1-DQ12
S
D1-A
8
FPGA_TDO
FPGA_TM
S
A
S
DO
nC
S
O
S
D1-DQ15
S
D1-DQ16
S
D1-DQM
DV-CLK
nCONFIG
CONF-DONE
DATA0
DCLK
M
S
EL1
FPGA_TCK
FPGA_TDI
I_17501_029.ep
s
29070
8
3
1
3
9 12
3
6
3
09.
3
B09D
B09D