Circuit Diagrams and PWB Layouts
63
7.
SSB: STI7100 Debug
V+
V-
VCC
C1+
C1-
C2+
T2
T1
IN
IN
OUT
OUT
GND
T1
C2-
R2
R1
T2
R1
R2
7AM1-1 E
3
7AM0 B
3
FAM1 C5
7AM1-2 G
3
9AM1 E2
9AM0 E5
9AM2 G
3
FAM2 C5
FAM0 C5
FAM
3
E5
FAM9 F5
FAMA F5
FAMB F5
FAME F5
FAMJ E5
S
TI7100: DEBUG
FAM4 E5
FAM5 E5
S
T40 DEBUG LINK
FAM6 E5
IAM2 C
3
IAM1 C
3
FAM
8
F5
FAM7 F5
IAM
3
C4
2AM0 B4
3
AM0 E5
1AM2 E5
G
2AM2 C4
2AM4 C2
1AM0 C5
2AM1 C2
2AM
3
C4
3
AM1 C2
3
AM2 C4
3
AM
3
C4
3
AM4 G
3
3
AM7 E4
3
AM
8
G4
F
RE
S
D
C
4
5
G
1
F
6
A
3
2
R
S
2
3
2 FOR MPEG4
E
B
6
RE
S
5
1
2
4
3
A
B
C
D
E
FAMB
9AM2
+
3
V
3
+
3
V
3
FAM0
FAMJ
9
11
14
10
7
2
6
16
1
3
4
5
15
1
3
12
8
Φ
R
S
2
3
2
S
T
3
2
3
2C
7AM0
FAME
+
3
V
3
10K
3
AM7
2AM2
100n
FAM6
FAM7
IAM1
IAM2
100n
FAM2
2AM4
100n
2AM1
10K
100n
3
AM4
+
3
V
3
2AM0
FAM4
FAM5
FAM
3
100R
+
3
V
3
3
AM1
10K
3
AM
8
100R
3
AM
3
100R
14
4
3
AM2
74LVC07APW
7AM1-2
3
7
74LVC07APW
7AM1-1
1
71
4
2
9AM1
FAM1
FAMA
FAM
8
FAM9
3
AM0
33
R
9AM0
RE
S
2AM
3
100n
20
3
4
5
6
7
8
9
11
12
1
3
14
15
16
17
1
8
19
2
5-147279-5
1AM2
1
10
1AM0
B
3
B-PH-
S
M4-TBT(LF)
1
2
3
4
5
IAM
3
TXD-A
S
C2
BUF-R
S
T-TARGETn
JTAG-TDI-
S
T
JTAG-TDO-
S
T
R
S
T-TARGETn
JTAG-TR
S
Tn-
S
T
TRIG-OUT
TRIG-IN
JTAG-TM
S
-
S
T
A
S
EBRKn
JTAG-TCK-
S
T
RXD-A
S
C2
B0
3
I
B0
3
I
H_17650_012.ep
s
171207
3
1
3
9 12
3
6
3
41.1