Philips FM242, Service Manual

Page: 73 / 90

Circuit Descriptions and List of Abbreviations EN 73 FM242 AA 9.
• YPbPr/RGB (combined 2fH and 1fH): named AV3 and
suitable for YCbCr/HD-YPbPr/HD-RGB + HV. These are
cinch inputs. YPbPr and RGB are seen as separate inputs
by the HW and must be properly selected by SW.
• CVBS like (1fH): named AV1 for CVBS and AV2 for Y/C.
These are also cinch inputs.
Video Path
The 1fH signals (including YPbPr) are buffered (item 7113/21/
17) and go directly to a digital video processor, the SAA7118E
(item 7225 on diagram SC5), where they are converted into a
digital signal.
The 2fH signals are also buffered; both YPbPr (item 7074/84/
79) and RGB (item 7141/38/35) buffers get the same input
signals.
When YPbPr signals are connected, the correct input must be
selected, to get a picture with proper colours. Thus, the signals
must pass a video matrix (item 7088/90, see diagram SC3),
where they are converted into RGB. There are two matrices, an
NTSC and an ATSC. With the MATRIX_SEL signal, the correct
matrix is chosen (item 7089). The detection is done automatic,
by an algorithm in the EPLD.
After the matrix, the signals enter a clamp/blanking circuit
(7102/03/04 and 7100), for the removal of the residual sync
signals. The control is done via the lines HD_BLANKN and
HD_CLAMPN coming from the EPLD.
All RGB signals come together at 4-pole switches (item 7146/
58), one for each colour, where they are switched to the AD
converter item 7170 (R_ADC, G_ADC and B_ADC).
Sync Path
All incoming H and V sync signals go to a 4-pole switch (item
7009) where SYNC_SEL and VIDEO_SEL_2 determine, which
signal is available on the ADC.
Before this switch, the VGA sync path is rather straight, only 1
switch (item 7007) is added for the VGA2 sync signals, which
determines if VGA2 sync is input or output (VGA2_OUT).
In the Basic configuration, these switches are omitted, and
replaced by jumpers (4009/4010).
The external sync (AV1 - 3) signals are treated differently. Both
H_HD_EXT and V_HD_EXT go to three circuits:
•
A comparator circuitry with an LM319 (item 7025), to
ensure both sync pulses are always positive going (H and
V_SYNC_CMP),
• A level detection circuitry (items 7000 to 7002), to detect if
the sync is of TTL level (H and V_SYNC_TTL),
• A positive/negative going detection circuitry (items 7006 to
7010), to indicate the polarity of the sync in case of TTL
level (H and V_SYNC_POL_N).
All above-mentioned signals go to the EPLD (see also diagram
SC11) for further processing.
Processed sync signals H_HD and V_HD coming from the
EPLD, are also switched to the ADC (H_ADC and V_ADC)
along with the proper RGB signals (R_ADC, G_ADC and
B_ADC).
Digital Video
This part describes the digital video path on the SCAVIO panel,
starting at the AD converters in either the AD9887 (item 7170)
or in the SAA7118E (item 7225) and ending at the output for the
PDP.
For both the Basic as the Enhanced version, everything 'after'
the PixelWorks chip, is equal.
For the Basic version, the input for the PixelWorks only
consists of the 'Graphics path'.
For the Enhanced version, it is both the 'Graphics path' as the
'Video path'.
The SCAVIO panel contains the following functions in the video
path:
1. The 'YPbPr to RGB matrix' and '2fH Video+Sync Switch'
are explained above in the 'Analogue Video' part.
2. The 'Digital Video' path containing the Digital Video
Decoder and the De-interlacer.
3. The 'Digital Graphics' path containing the ADC+TMDS
decoder.
4. The 'Scaler' which is the PixelWorks (PW164-10R) plus
Memory.
5. The 'EPLD' for sync decoding and video manipulation.
6. The 'LVDS' encoder.
The Digital 'Graphics Path'
This is a straightforward application of the Analogue Devices
AD9887 (item 7170). Inputs for this device are:
•
FTV Receiver box,
• VGA formats (up to SXGA@75 Hz),
• 2fH RGB+HV (only in Enhanced version),
• 2fH YPbPr, which is converted to RGB by the 'YUV to RGB'
matrix (only in Enhanced version),
• DVI-d (only in Enhanced version).
Analogue input: The AD9887 is meant to sample 'pixel
synchronous'. To achieve this, a (software) driver is running on
the PixelWorks processor (PW). After hooking up a source to
the AD9887, the PW starts counting the number of lines per
field and calculates the H-period time. With these two values, it
determines the exact match or the closest match out of a look-
up-table (LUT) with VGA standards. When the correct standard
is determined, the PW will set the AD9887 I
2
C registers to the
correct value. The AD9887 should now sample with exact the
same frequency as the incoming standard requires. This is
done to get an optimal picture performance.
It also is a 'must' when a computer graphics card is connected,
because there is no, or very little, post anti-aliasing filtering
done on such cards. Therefore, the outputted RGB samples
need to be exactly aligned with the sampling of the AD
converter.
Analogue input signals can go up to SXGA@75 Hz, which
gives a pixel clock of 135 MHz. In fact, it can handle any
standard with a pixel rate up to 140 MHz.
Special modes are made for the F21R E-box, for both PAL and
NTSC. These are invoked when an E-box is connected to the
SCAVIO panel.
Digital input: Via the DVI connector (Enhanced version only)
it is possible to insert TMDS (Transition Minimised Differential
Signalling) data into the SCAVIO panel. DVI is a fairly new
computer graphics standard, which can be seen as the digital
follow-up of the analogue VGA interface. The TMDS signal is
directly fed into the AD9887, where any DVI standard up to
SXGA@60 Hz can be decoded to RGBHV.
The preferred VGA standard for the FM242 is programmed in
the DDC EEPROM (item 7215), which can be read by the PC.
Via an internal switch, it is possible to choose between the
analogue input and the digital input. The output format is for
both inputs the same (8 bit RGB plus HV). The driver
determines whether the AD9887 outputs single or dual pixels.
For lower standards like VGA@60Hz, the interface will be
single pixel, which means that every clock cycle one byte of R,
G, and B data is outputted. Dual pixel means that on every
clock cycle two bytes of R, G, and B data outputted. These two
bytes are de-multiplexed, which is done to make the interface
more robust for jitter, set-up, and hold times, and to reduce the
digital data rate over the PCB (reduced EMC).
Digital 'Video Path'
This path is only available in the Enhanced version of the
SCAVIO panel and is used for the following input signals:
•
CVBS input,
• Y/C input, and
• 1fH YPbPr.
It is a straightforward application of the Philips SAA7118 (item
7225) and the Micronas SDA9400 (item 7280).