1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A
A
B
B
C
C
D
D
E
E
F
F
TERMINATION AT DDR
TERMINATION AT E5.1
VREF should be routed over a
reference plane and isolated, and possibly
shielded with both SSTL2_VDD and SSTL2_GND
VREF needs to be decoupled
to both SSTL2_VDD and SSTL2_GND with balanced
decoupling capacitors.
DDR TERMINATION VOLTAGE REGULATOR
The VTT side of the terminaton resistors should be placed
on a wide VTT island on the surface layer. The island is
located at each end of the bus, so it does not interfere
with the signal routing.
C111 B3
C112 B3
C115 B3
C116 B3
C119 B3
C120 B3
C124 C3
C123 C3
C128 E3
C127 E5
C129 C3
C130 C3
C133 C5
C135 D3
C136 D3
C139 D5
C279 C3
C280 C3
C281 C3
C282 C3
C283 C4
C284 D4
C285 D3
C286 D3
C287 D3
C288 D4
C290 B4
C291 B4
C292 B4
C295 B4
C294 B4
C297 B4
C296 B4
C298 E5
C299 E5
C300 C4
C301 C4
C302 C4
C303 C4
C315 E5
C319 C4
C320 C4
C321 C4
C322 C5
C323 C5
C324 D4
C325 D4
C326 D4
C327 D5
C328 D5
C329 E5
CA28 E5
CA29 E4
R5 E1
R6 E1
R8 E1
R10 E1
R11 E6
R13 E1
R14 E1
R17 E6
R16 E1
R15 E6
R18 E1
R20 E6
R21 E6
R19 E6
R22 E6
R23 E6
R27 E1
R24 E6
R31 E6
R162 E6
R164 E6
R442 E6
R168 E6
R444 E6
R443 E6
RP7 A6
RP8 D6
RP9 B6
RP10 D6
RP11 B6
RP12 D6
RP13 B6
RP14 D6
RP15 C6
RP17 C6
RP18 C6
RP19 B6
RP20 A1
RP21 B1
RP22 B1
RP23 C1
RP24 C1
RP26 B1
RP35 C1
RP32 C1
RP28 B1
RP43 D1
RP44 D1
RP45 D1
RP47 D1
RP48 E1
U26 E4
SDRAM_DQ16
SDRAM_DQ6
SDRAM_A11
SDRAM_DQ14
E5_SDRAM_DQ24
SDRAM_DQ23
SDRAM_DQ27
SDRAM_CLK1
SDRAM_DQ0
SDRAM_DQ5
GND_SSTL2
SDRAM_DQ18
E5_SDRAM_DQ21
SDRAM_A15
SDRAM_DQ8
SDRAM_CAS#
E5_SDRAM_DQ14
E5_SDRAM_DQ7
GND_SSTL2
SDRAM_DQ31
E5_SDRAM_DQ15
E5_SDRAM_DQ4
SDRAM_DQ29
SDRAM_DQ10
SDRAM_DQ11
GND_SSTL2
SDRAM_CLK#1
E5_SDRAM_DQ8
SDRAM_DQ3
SDRAM_DQ22
SDRAM_DQ19
GND_SSTL2
SDRAM_DQ19
SDRAM_A4
SDRAM_DQ3
GND_SSTL2
SDRAM_DQ6
E5_SDRAM_DQ30
SDRAM_DQ22
E5_SDRAM_DQ26
SDRAM_DQ16
SDRAM_DQ15
SDRAM_DQ13
SDRAM_A8
VTT
E5_SDRAM_DQ9
E5_SDRAM_DQ0
SDRAM_DQ1
E5_SDRAM_DQ18
SDRAM_DQM1
SDRAM_DQS3
E5_SDRAM_DQ11
SDRAM_DQ25
E5_SDRAM_DQ27
SDRAM_DQ2
VREF
SDRAM_DQ4
VREF
E5_SDRAM_DQ5
SDRAM_DQ17
E5_SDRAM_DQ25
SDRAM_DQ28
SDRAM_DQ30
SDRAM_DQ20
E5_SDRAM_DQ28
SDRAM_DQ23
SDRAM_DQ18
SDRAM_DQS0
VTT
SDRAM_DQ11
SDRAM_DQ9
E5_SDRAM_DQ16
SDRAM_DQ26
SDRAM_A7
SDRAM_WE#
SDRAM_RAS#
SDRAM_DQ21
SDRAM_A12
E5_SDRAM_DQ12
E5_SDRAM_DQ10
SDRAM_DQ2
SDRAM_DQ31
SDRAM_DQS1
SDRAM_DQ14
VREF
SDRAM_CLK0
SDRAM_CS0
SDRAM_DQ26
SDRAM_DQ25
SDRAM_DQ4
SDRAM_A6
SDRAM_A3
SDRAM_CLK#0
SDRAM_DQ12
SDRAM_DQ29
E5_SDRAM_DQ1
SDRAM_DQM0
E5_SDRAM_DQ17
E5_SDRAM_DQ31
E5_SDRAM_DQ19
SDRAM_DQ21
SDRAM_DQ13
SDRAM_A9
E5_SDRAM_DQ13
SDRAM_DQ1
SDRAM_DQ5
SDRAM_DQS2
SDRAM_A0
SDRAM_A2
E5_SDRAM_DQ29
E5_SDRAM_DQ22
SDRAM_DQM3
SDRAM_DQ9
SDRAM_CLKE
SDRAM_DQ28
SDRAM_DQ7
SDRAM_A1
SDRAM_A10
SDRAM_DQ8
SDRAM_DQ12
SDRAM_A14
E5_SDRAM_DQ20
E5_SDRAM_DQ3
SDRAM_DQ30
SDRAM_DQ27
SDRAM_DQ20
E5_SDRAM_DQ23
SDRAM_DQ0
SDRAM_DQ24
SDRAM_DQM2
SDRAM_DQ17
SDRAM_A5
E5_SDRAM_DQ6
SDRAM_DQ24
E5_SDRAM_DQ2
SDRAM_DQ7
SDRAM_DQ10
SDRAM_DQ15
SDRAM_DQS0
E5_SDRAM_DQM2
E5_SDRAM_A3
SDRAM_CLK#1
VREF
E5_SDRAM_A14
SDRAM_A8
E5_SDRAM_A1
SDRAM_A0
SDRAM_CLK#0
E5_SDRAM_A10
SDRAM_CLKE
E5_SDRAM_A8
E5_SDRAM_CLK1
SDRAM_DQM0
SDRAM_CAS#
E5_SDRAM_A12
SDRAM_A12
E5_SDRAM_A6
E5_SDRAM_CLK#1
SDRAM_A9
E5_SDRAM_A5
E5_SDRAM_A9
E5_SDRAM_DQM1
SDRAM_A5
SDRAM_A1
SDRAM_WE#
E5_SDRAM_DQ[31..0]
E5_SDRAM_A0
E5_SDRAM_WE#
E5_SDRAM_DQM0
SDRAM_DQM3
SDRAM_DQM1
SDRAM_A14
SDRAM_A2
SDRAM_A7
E5_SDRAM_A7
SDRAM_A11
SDRAM_A15
E5_SDRAM_A11
SDRAM_DQS2
VREF
E5_SDRAM_DQM3
E5_SDRAM_CLKE
VREF
SDRAM_CLK1
SDRAM_DQM2
SDRAM_DQ[31..0]
E5_SDRAM_A2
E5_SDRAM_CAS#
E5_SDRAM_DQS3
SDRAM_A6
E5_SDRAM_CLK0
SDRAM_A3
E5_SDRAM_DQS2
E5_SDRAM_CS0
SDRAM_RAS#
E5_SDRAM_A15
E5_SDRAM_RAS#
E5_SDRAM_CLK#0
SDRAM_CLK0
SDRAM_DQS3
E5_SDRAM_DQS1
E5_SDRAM_A4
SDRAM_DQ[31..0]
SDRAM_CS0
SDRAM_A4
E5_SDRAM_DQS0
SDRAM_A10
SDRAM_DQS1
SSTL2_VDD
VTT
VTT
SSTL2_VDD
SSTL2_VDD
SSTL2_VDD
VTT
SSTL2_VDD
VTT
RP44 22/RP
1
8
2
7
3
6
4
5
C327
1000PF
RP19 51/RP
1
8
2
7
3
6
4
5
RP26 51/RP
1
8
2
7
3
6
4
5
RP43 22/RP
1
8
2
7
3
6
4
5
R20
51
C130
0.1UF
RP28 51/RP
1
8
2
7
3
6
4
5
C120
0.1UF
RP21 51/RP
1
8
2
7
3
6
4
5
RP8
51/RP
1
8
2
7
3
6
4
5
R27
22
RP22 51/RP
1
8
2
7
3
6
4
5
C129
0.1UF
RP23 51/RP
1
8
2
7
3
6
4
5
R162
51
RP35 22/RP
1
8
2
7
3
6
4
5
RP24 51/RP
1
8
2
7
3
6
4
5
R164
51
C324
1000PF
+
CA29
220UF/10V
RP32 51/RP
1
8
2
7
3
6
4
5
C319
1000PF
RP10 51/RP
1
8
2
7
3
6
4
5
R19
51
C282
0.01UF
C287
0.01UF
C115
0.1UF
+
CA28
220UF/10V
C281
0.01UF
C290
0.01UF
C286
0.01UF
C283
0.1UF
R13
22
C292
0.01UF
C291
0.01UF
C288
0.1UF
R14
22
U26
LP2995
1
2
3
4
5
6
7
8
NC
GND
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
R31
51
R16
22
R444
51
RP48
22/RP
1
8
2
7
3
6
4
5
C135
0.1UF
C133
0.1UF
R18
22
C280
0.1UF
C315
0.1UF
R17
51
R443
51
R21
51
C326
1000PF
C321
1000PF
C294
0.01UF
R22
51
C295
0.01UF
R8
51
C127
0.1UF
RP47 22/RP
1
8
2
7
3
6
4
5
C112
0.1UF
C123
0.1UF
C300
0.01UF
R24
51
C136
0.1UF
C301
0.01UF
R10
51
C124
0.1UF
+
C298
10UF/6V/A
C296
0.1UF
R23
51
C297
0.1UF
R6
51
RP12
51/RP
1
8
2
7
3
6
4
5
C285
0.1UF
C328
1000PF
C302
0.1UF
+
C299
10UF/6V/A
C279
0.1UF
C323
1000PF
C303
0.1UF
RP14 51/RP
1
8
2
7
3
6
4
5
R5
51
C284
0.1UF
C116
0.1UF
RP11 51/RP
1
8
2
7
3
6
4
5
RP15 51/RP
1
8
2
7
3
6
4
5
RP18
51/RP
1
8
2
7
3
6
4
5
C325
1000PF
RP20 51/RP
1
8
2
7
3
6
4
5
C320
1000PF
RP7 51/RP
1
8
2
7
3
6
4
5
RP9
51/RP
1
8
2
7
3
6
4
5
C119
0.1UF
R15
51
C128
0.1UF
RP13 51/RP
1
8
2
7
3
6
4
5
C329
0.1UF
RP17
51/RP
1
8
2
7
3
6
4
5
C139
0.1UF
R11
51
RP45 22/RP
1
8
2
7
3
6
4
5
R442
51
R168
51
C322
1000PF
C111
0.1UF
6-12
6-12
DVDR3408/93 Main Board Eletrical Diagram: TERM AT E5 & DDR & VREF/VT
Title:TERM AT E5 & DDR & VREF/VT
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