16
DP-IF8000
Pin No.
Pin name
I/O
Description
49
VCCQH
I
Power supply terminal.
50
FST1
I
Receiver frame sync signal input.
51
AA2
—
Not used (OPEN).
52
CAS
—
Not used (OPEN).
53
DE
I
Transmitter serial clock signal input.
54
CNDQ
—
Ground terminal.
55
EXTAL
I
Exterminal clock signal input (12,2888MHz).
56
VCCQL
I
Power supply terminal.
57
VCCC
I
Power supply terminal.
58
GNDC
—
Ground terminal.
59
FSR1
I
Receiver frame sync signal input.
60
SCKR1
I
Transmitter serial clock signal input.
61
PINIT
—
Ground terminal.
62
TA
—
Ground terminal.
63
BR
—
Not used (OPEN).
64
BB
I
Bus busy signal input.
65
VCCC
I
Power supply terminal.
66
GNDC
—
Ground terminal.
67
WR
—
Not used (OPEN).
68
RD
—
Not used (OPEN).
69 • 70
ADD1 •
0
—
Not used (OPEN).
71
BG
—
Ground terminal.
72 • 73
A0 • 1
—
Not used (OPEN).
74
VCCA
I
Power supply terminal.
75
GNDA
—
Ground terminal.
76 to 79
A2 to 5
—
Not used (OPEN).
80
VCCA
I
Power supply terminal.
81
GNDA
—
Ground terminal.
82 to 85
A6 to 9
—
Not used (OPEN).
86
VCCA
I
Power supply terminal.
87
GNDA
—
Ground terminal.
88 to 89
A10 • 11
—
Not used (OPEN).
90
GNDQ
—
Ground terminal.
91
VCCQL
I
Power supply terminal.
92 to 94
A12 to 14
—
Not used (OPEN).
95
VCCQH
I
Power supply terminal.
96
GNDA
—
Ground terminal.
97 to 99
A15 to 17
—
Not used (OPEN).
100 to 102
D0 to 2
—
Ground terminal.
103
VCCD
I
Power supply terminal.
104
GNDD
—
Ground terminal.
105 to 110
D3 — 8
—
Ground terminal.
111
VCCB
I
Power supply terminal.
112
GNDD
—
Ground terminal.
113 to 118
D9 — 14
—
Ground terminal.
119
VCCD
I
Power supply terminal.
120
GNDD
—
Ground terminal.
121 to 125
D15 — 19
—
Ground terminal.
• IC19 XCB56467PV150 (24 BIT AUDIO DIGITAL SIGNAL PROCESSOR) (2/3)
Summary of Contents for DP-IF8000
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