130
7.
Circuit Diagrams and PWB Layouts
SSB: PNX5100: Control
TDI
TDO
RE
S
ET_
S
Y
S
S
DA
S
CL
S
DA
S
CL
RX
TX
RX
TX
XTAL
UA1
UA2
1
2
TM
S
TR
S
T
NC
RE
S
ET_IN
OUT2
OUT
IN
VPP_ID
OB
S
ERVE
TCK
S
CL
ADR
0
1
2
S
DA
WC
A
B
C
D
1CD0 A2
2CD0 A2
2CD1 A2
3
CD0 B2
3
CD1-1 C2
3
CD1-2 C2
3
CD1-
3
C2
3
CD1-4 C1
3
CD2 C2
3
CD7 B5
3
CD
8
B5
6
7
1
2
3
4
5
6
7
A
B
C
D
only for DEBUG
1
2
3
4
5
C0
8
OR C16
FCD6 D5
FCD
8
B
3
ICD
8
B
3
3
CD9 B5
3
CDA B5
3
CDB D7
3
CDC D6
3
CDD D6
PNX5100: CONTROL
7C00-1 A
3
7CD0 C4
9CD0 D7
FCD0 B
3
FCD1 B
3
FCD2 B
3
FCD
3
B
3
FCD4 B
3
3
CDC
100R
3
CD1-
3
10K
ICD
8
+
3
V
3
27M
1CD0
2CD0
27p
+
3
V
3
FCD
8
100R
3
CD0
3
CD2
10K
3
CDD
100R
3
CD
8
+
3
V
3
+
3
V
3
100R
FCD
3
3
CDB
+
3
V
3
+
3
V
3
4K7
3
CD7
100R
AD
8
AC
8
AB21
AE1
3
AF1
3
AF14
K2
L2
K1
L1
H4
H2
H
3
J1
J2
AF
8
AE
8
G22
H22
W22
Y22
R1
AF24
AD12
PNX5100E
7C00-1
Φ
CONTROL
27p
2CD1
FCD1
FCD2
3
CD9
100R
RE
S
FCD4
RE
S
4
7
100R
3
CDA
7CD0
M24C16-WDW6
1
2
3
6
5
8
(2Kx
8
)
Φ
EEPROM
+
3
V
3
FCD6
FCD0
10K
3
CD1-4
3
CD1-1
10K
10K
3
CD1-2
9CD0
S
CL-
SS
B
WC-EEPROM-PNX5100
S
CL-
SS
B
S
DA-
SS
B
WC-EEPROM-PNX5100
S
DA-
SS
B
S
CL-DI
S
P
S
DA-DI
S
P
RE
S
ET-PNX5100
PNX5100-R
S
T-OUT
EJTAG-PNX5100-TR
S
Tn
CLK-OUT-PNX5100
EJTAG-PNX5100-TCK
EJTAG-PNX5100-TDI
EJTAG-PNX5100-TDO
EJTAG-PNX5100-TM
S
3
1
3
9 12
3
6214.4
I_17660_0
3
4.ep
s
110
3
0
8
B05F
B05F