110
7.
Circuit Diagrams and PWB Layouts
SSB: PNX
8
541: NVM
S
CL
ADR
0
1
2
S
DA
WC
D
E
F
3
H29 E1
3
H
33
E2
3
H
3
4 E2
1
2
3
H
3
5 F2
3
H40 E2
2
3
4
5
6
F
A
MAIN NVM
2H04 E
3
2H05 E
3
2H09 E1
2HC0 B4
3
H09 D1
7H05 E1
7HC
3
B4
7HC4 A4
9H07 D4
3
HC2-1 A
3
3
HC2-2 A
3
3
HC2-
3
B5
3
HC2-4 B
3
7H04 D
3
FHC6 A2
FHC7 C4
IH12 D2
IH21 B
3
IH
3
2 E2
FH0
3
E2
FH0
8
E
3
FH09 A
3
3
4
5
6
1
FHC1 B5
FHC2 B5
IHC1 B4
IHC2 A4
A
B
C
D
E
M24C64
C
B
PNX
8
541: NVM
9H07
2K2
3
H09
RE
S
FHC2
A
3
1
K
R
2
FH09
T
S
24
3
1
7H05
7HC4
BC
8
57BW
8
4
7
7HC
3
1
2
3
6
5
(
8
Kx
8
)
Φ
EEPROM
3
6
FH0
8
+5V5-TUN
10K
3
HC2-
3
IH
3
2
1
u
0
2H05
2H04
1
u
0
3
H
3
4
1K0
3
H
33
1K0
2H09
22n
1
3
PHD
38
N02LT
7H04
2
+5V-TUN
3
H40
10K
+12VD
RE
S
+
3
V
3
-PER
FHC7
FH0
3
2HC0
100n
IH12
RE
S
IHC1
IH21
FHC1
3
HC2-2
10K
72
3
H29
10K
FHC6
IHC2
3
H
3
5
45
1K0
1
8
+
3
V
3
-PER
10K
3
HC2-4
10K
3
HC2-1
S
CL-UP-MIP
S
S
DA-UP-MIP
S
RE
S
ET-NVM
3
1
3
9 12
3
6214.4
I_17660_015.ep
s
110
3
0
8
B04C
B04C