Service Modes, Error Codes, and Fault Finding
5.
Figure 5-6 “Off” to “Semi Stand-by” flowchart (part 3)
Yes
Semi-Standby
initialize tuner , Master IF and channel
decoder according FMS information
Initialize video processing IC 's according FMS information:
- PNX5050 in /82
- scaler EPLD
Initialize source selection according FMS
and CHS information
initialize AutoTV by triggering CHS AutoTV Init interface
See appropriate CHS documents for further details.
3-th try?
Blink Code as
error code
SP
Switch POD-MODE and ON-MODE
I/O line high.
switch off the remaining DC/DC
converters
Do not enter semi-standby state in case of an LPL
scanning backlight LCD set before 4s preheating timer has
elapsed.
Initialize Ambilight with Lights off .
Initialize Pacific or EPLD related Ambilight
settings (if applicable)
Pacific acknowledges ?
Ping the Pacific through I²C
Reset the Pacific by pulling LOW the Pacific
hardware reset line during 100ms.
Release Pacific reset
and wait 200ms
Third Pacific boot retry?
No
No
Yes
Log Pacific error
Yes
Enable the Pacific output by sending the PanelConfig.PanelOn
to the Pacific
in case of a DFI set
This is needed here because the Pacific has to
deliver an output clock towards the DFI. Otherwise
the DFI cannot deliver ambilight functionality in the
lampadaire mode. The presence of the DFI can be
determined via the display option.
Downloaded
successfully ?
Download firmware into the channel
decoder
Third try?
No
No
Yes
Log channel decoder error
Yes
Channel decoder
TDA 10048?
Yes
No
- Channeldecoder type TDA10060
cannot be reloaded without reset
of the channeldecoder.
- Channeldecoder type TDA10048
can be reloaded without reset.
Initialize audio according FMS information:
Start 4 seconds preheating timer
in case of
an LPL scanning backlight LCD set
.
Init Pacific according use case :
- lvds or CMOS input and output
- panel config…
to be discussed with Stefan / SW if we will put this here or in
the display excel overview of Stefan or in …..
Power-ok display high ?
No
Yes
Log power-ok error and enter
protection
MP
Wait until Cpipe delivers a stable output
clock
Reset EPLD
Wait 100ms
Reset Pacific clock
EPLD
and
Pacific
should
be reset
when a
stable
input
clock
become
s
available
at their
input.
H_16770_109c.eps
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