Philips CE130/55 Service Manual Download Page 64

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FEDD56V16160F-02

Semiconductor

MSM56V16160F

22/31

Read to Write Cycle (Same Bank) @

CAS

Latency=2, Burst Length=4

*Note: 1. In Case

CAS

latency is 3, READ can be interrupted by WRITE.

The minimum command interval is [burst 1] cycles.
UDQM, LDQM must be high at least 3 clocks prior to the write command.

CLK

CKE

RAS

CAS

ADDR

A11

A10

UDQM,

LDQM

10 11 12 13 14 15 16 17 18 19

Ca0

Cb0

Db0 Db1

∗

Note 1

Row Active

Read Command

Write Command

Precharge Command

RCD

Db2 Db3

Da0

Summary of Contents for CE130/55

Page 1: ...ut diagram Main board 9 10 Panel board 11 12 Tuner board 13 14 Mechanical Exploded view 15 Copyright 1 Philips Consumer Electronics B V Eindhoven The All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying or otherwise without the prior permission of Philips Published by LX 1145 Ser...

Page 2: ...d Dynamic Bass Boost Output power MAX 45Wx4 channels Output power RMS 22Wx4 channels 4 ohms 10 T H D Connectivity USB USB 2 0 Host Memory card SD SDHC MP3 Link For portable MP3 music playback Preamp output 2 pairs RCA L R Security Anti thief Front panel Detachable Display blackout 10 20 sec selectable Accessories Remote control Not included User Manual Brazilian Portuguese Quick start guide Brazil...

Page 3: ...15kHz e g 7122 707 48001 LF Voltmeter e g PM2534 DUT S N and distortion meter e g Sound Technology ST1700B Frame aerial e g 7122 707 89001 Tuner AM MW LW To avoid atmospheric interference all AM measurements have to be carried out in a Faraday s cage Use a bandpass filter or at least a high pass filter with 250Hz to eliminate hum 50Hz 100Hz RF Generator e g PM5326 Ri 50 Bandpass 250Hz 15kHz e g 71...

Page 4: ...ng make sure that you are connected with the same potential as the mass of the set via a wrist wrap with resistance Keep components and tools also at this potential ESD CLASS 1 LASER PRODUCT GB Safety regulations require that the set be restored to its original condition and that parts which are identical with those specified be used Safety components are marked by the symbol Lead free ...

Page 5: ...T OK check playability N Y playability ok check playability check playability return set Customer complaint CD related problem fast lens cleaning 1 2 3 For flap loaders access to CD drive possible cleaning method 4 is recommended INSTRUCTIONS ON CD PLAYABILITY 2 1 Exchange CDM 1 4 For description see following pages ...

Page 6: ...viously caused by a scratched dirty or copy protected CD In case problems remain the customer is requested to contact the workshop directly The lens cleaning method 3 should be mentioned in the addendum sheet The final wording in national language as well as the printing is under responsibility of the Regional Service Organizations 4 LIQUID LENS CLEANING Because the material of the lens is synthet...

Page 7: ...er A 3 Remove cover on unit 4 Remove 6pcs 2X6BTP screw on panel button cover B 5 Detach the button cover Note put on static belt during operation and keep yourself from electronic screw driver static A Main B 1 2 3 4 面咀 KB板面咀 KB板 Panel Handy back 5 DISMANTLING INSTRUCTIONS ...

Page 8: ...3 BLOCK DIAGRAM ...

Page 9: ...4 WIRING DIAGRAM ...

Page 10: ...5 CIRCUIT DIAGRAM MAIN BOARD ...

Page 11: ...6 CIRCUIT DIAGRAM MAIN BOARD ...

Page 12: ... R947 NC R948 390 R949 NC R950 390 R951 NC R952 270 R953 NC C902 104 LED21 LED R961 270 R964 0R EN901 EN SW24 POWER MUTE C905 2P ZR901 22P ZR902 22P EC901 10uF Q905 NC R965 NC R966 NC 1 2 3 4 USBIN USB C903 2P C906 2P C908 2P R975 270 R976 NC R955 390 R954 NC R956 390 R957 NC R969 270 R970 NC R971 390 R972 NC R967 270 R968 NC R973 270 R974 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 2...

Page 13: ...C106 104 C105 474 C110 474 L104 220UH C107 1U L105A 1MH C109 183 C101 30P L101 FB 1 5K S G D Q102 MF862 S G D Q103 MF862 L102 220NH 1 2 ANT ANT R100 47 R4 10K C123 47P L106 33UH 1 2 3 4 Q104 3SK254 C118 15P C120 15P L103 220NH C121 30P L107 2 7UH R101 270K C122 223 C108 104 C1 47uF 16V C114 2U2 C113 102 R104 NC 12 1 2 3 4 6 7 8 9 10 5 11 CON103 CON 12P TUNER CLK TUNER DA TUNER RES CHGND CHGND XOUT...

Page 14: ...MAIN PCB COMPONENT LAYOUT TOP SIDE VIEW 9 ...

Page 15: ...MAIN PCB COMPONENT LAYOUT BOTTOM SIDE VIEW 10 ...

Page 16: ...PANEL PCB COMPONENT LAYOUT TOP SIDE VIEW 11 ...

Page 17: ...PANEL PCB COMPONENT LAYOUT BOTTOM VIEW PANEL PCB COMPONENT LAYOUT BOTTOM VIEW 12 ...

Page 18: ...TUNER PCB COMPONENT LAYOUT TOP SIDE VIEW 13 ...

Page 19: ...TUNER PCB COMPONENT LAYOUT BOTTOM IDE S VIEW 14 ...

Page 20: ...SET EXPLODER VIEW DRAWING 15 ...

Page 21: ...of the tuner e Whether there is any cold solder of any component on the tuner f Whether where is any defective of IC1 4558 and the components around a Whether the power supply of UBS 5V is normal b Whether the connector of front panel have a good contact c Whether the socket of CON201 26P have buckled in place d Whether there is any cold solder of L207 L208 R713 R716 C703 C704 e Whether there is a...

Page 22: ...BX8804 8805 User s Manual Revision 0 93 May 23 2008 ...

Page 23: ...CON 0x88000C PLL1_LOCK refer 6 5 Add PLL3_CON 0x880014 PLL3_SEL PLL3_LOCK refer 6 5 Change reset value of DAC_CLK_CON 0x870048 refer 7 3 Register HU0CON 0x88A000 RFTL TFTL bit description modify refer 12 2 Register GPMODE0 0x884010 GP02MODE description modify refer 15 2 Add electrical characteristics of USB refer 21 2 0 93 May 23 2008 Correct PLL power pins of pin configuration refer Figure 1 ...

Page 24: ...DRESS MAP 26 3 1 OVERVIEW 27 3 2 MEMORY MAP 27 4 CPU 29 4 1 PROCESSOR OPERATING STATES 30 4 1 1 SWITCHING STATE 30 4 2 MEMORY FORMATS 30 4 3 DATA TYPES 31 4 4 OPERATING MODES 31 4 5 REGISTERS 31 4 5 1 THE ARM STATE REGISTER SET 32 4 5 2 THE THUMB STATE REGISTER SET 34 4 5 3 THE RELATIONSHIP BETWEEN ARM STATE AND THUMB STATE REGISTERS 35 4 5 4 ACCESSING HIGH REGISTERS R8 R15 IN THUMB STATE 35 4 6 T...

Page 25: ...A FORMAT 66 8 3 CD DSP INTERFACE MODE 67 8 4 CD DSP INTERFACE REGISTERS 69 9 USB CONTROLLER 75 9 1 THE USB HOST CONTROLLER 76 9 1 1 OPERATION REGISTER 76 9 1 2 THE CONTROL AND STATUS PARTITION 76 9 1 3 MEMORY POINTER PARTITION 83 9 1 4 FRAME COUNTER PARTITION 85 9 1 5 ROOT HUB PARTITION 87 9 2 THE USB DEVICE CONTROLLER 94 9 2 1 REGISTERS 94 9 2 2 ENDPOINT BUFFERS 95 9 2 3 USB 1 1 DEVICE REGISTERS ...

Page 26: ...C OPERATION 229 18 4 2 GENERAL CHARACTERISTICS 230 18 4 3 BIT TRANSFERS 231 18 4 4 DATA VALIDITY 231 18 4 5 START AND STOP CONDITION 231 18 4 6 WAIT STATE PROCEDURE 231 18 4 7 START BYTE PROCEDURE 232 18 4 8 ARBITRATION PROCEDURE 232 18 5 DATA TRANSFER OPERATION 233 18 5 1 DATA BYTE FORMAT 233 18 5 2 ACKNOWLEDGE PROCEDURE 233 18 5 3 DATA TRANSFER FORMAT 234 18 5 4 I2C ADDRESSING 234 18 5 5 DEFINIT...

Page 27: ... INTERFACE CASE 2 68 FIGURE 13 CD DSP INTERFACE CASE 3 68 FIGURE 14 CD DSP INTERFACE CASE 4 68 FIGURE 15 BAUD CLOCK 113 FIGURE 16 ORDINARY INFRA RED CHARACTER TIMING DIAGRAM 114 FIGURE 17 INTERRUPT BASED SERIAL I O TRANSMIT RECEIVE TIMING DIAGRAM 115 FIGURE 18 TIMER STRUCTURE 148 FIGURE 19 INTERRUPT STRUCTURE 197 FIGURE 20 I2C MASTER TRANSMITTER AND SLAVE RECEIVER 230 FIGURE 21 I2C MASTER RECEIVER...

Page 28: ... CORE MEMORY MAP 47 TABLE 22 EXTENDED M BUS SYSTEM REGISTER MAP 47 TABLE 23 APB SYSTEM REGISTER MAP 47 TABLE 24 AVAILABLE LIST OF PLL1 AND PLL3 VALUE 49 TABLE 25 AVAILABLE LIST OF PLL2 VALUE 49 TABLE 26 SYSTEM CONFIGURATION REGISTERS 49 TABLE 27 SERIAL AUDIO DATA INTERFACE REGISTERS 62 TABLE 28 CD DSP INTERFACE REGISTERS 69 TABLE 29 THE CONTROL AND STATUS PARTITION REGISTERS 76 TABLE 30 MEMORY POI...

Page 29: ...BX8804 8805 8 21 TABLE 46 CO PROCESSOR COMMAND LIST 243 TABLE 47 DC CHARACTERISTICS 249 TABLE 48 USB CHARACTERISTICS 249 ...

Page 30: ...BX8804 8805 9 21 1 PRODUCT OVERVIEW ...

Page 31: ...ut Output ports In addition SRS WOW MP3 encoding and WMA encoding features are available as system solutions By utilizing advanced 0 13 micron technology the BX8805 is the perfect solution for digital audio products with low power requirements high performance and powerful processing in 144 TQFP and 128 TQFP packages 1 2 FEATURES Process z Low power 0 13 um CMOS technology z Core Supply power 1 2 ...

Page 32: ...oint 1152 byte FIFO z Compliant to USB 1 1 specification z Support FS Full Speed 12Mbps z Support Control Bulk ISO and Interrupt transfer Co processor and Functions z MPEG 1 2 2 5 layer2 and 3 decoding z Window Media Audio WMA V9 compatible decoding z Audio decoding of Window Media Video WMV z Advanced System Format ASF decoding z Ogg Vorbis by Q10 decoding z High quality MLPCM voice recording z M...

Page 33: ...mat z Joliet decoding both single session and multi session disc z Joliet Level 3 z UDF V1 02 V1 5 V2 01 z UDF in packet writing format z Sorting directories and files in name order z playing list file 1 3 APPLICATIONS z Portable MP3 WMA Ogg Player Flash or CD type z MP3 Juke box z Car Audio z Digital audio Encoder Decoder z Digital Internet Radio server z Multimedia Storage Device ...

Page 34: ...44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 ADIN3 ADIN4 PLL1VDD12 PLL1VSS12 PLL2VDD12 PLL2VSS12 PLL3VDD12 PLL3VSS12 USBVSS33 USBDM USBDP USBVDD33 VSS33 VDD33 XO XI TEST VSS33 NTRST RESETN GP36 GP35 GP34 GP33 GP32 GP31 GP30 GP29 TCK TMS TDO BX8805 ADIN2 Fig...

Page 35: ...9 D12 B External SDRAM data bus 12 External program data bus 12 20 D5 B External SDRAM data bus 5 External program data bus 5 21 D13 B External SDRAM data bus 13 External program data bus 13 22 D6 B External SDRAM data bus 6 External program data bus 6 23 D14 B External SDRAM data bus 14 External program data bus 14 24 D7 B External SDRAM data bus 7 External program data bus 7 25 D15 B External SD...

Page 36: ... address 19 General Purpose IO 39 58 EAD20 B External memory address 20 General Purpose IO 40 Booting Mode 59 EWEN B External memory WEN General Purpose IO 41 60 EOEN B External memory OEN General Purpose IO 42 61 ECSN O External memory CSN 62 GP03 B General Purpose IO 03 External Clock 16 9344MHz 63 GP04 B General Purpose IO 04 SPI0 CS 64 GP05 B General Purpose IO 05 SPI0 CK 65 GP06 B General Pur...

Page 37: ...GP24 B General Purpose IO 24 HUART1 DO 90 GP25 B General Purpose IO 25 External Interrupt 5 SPI2 CK 91 GP26 B General Purpose IO 26 External Interrupt 6 SPI2 MISO 92 GP27 B General Purpose IO 27 External Interrupt 7 SPI2 MOSI 93 GP28 B General Purpose IO 28 Wake UP When GP28 is used for WAKE UP signal input pin the external pull down resistor 48kΩ has to be connected with this pin 94 TDI B JTAG TD...

Page 38: ... for Reset of JTAG the external pull up resistor 48kΩ has to be connected with this pin 110 IOVSS33 P I O Ground 111 TEST I Test 112 XI I System clock input 113 XO O System clock output 114 IOVDD33 P I O Power supply 3 3V 115 IOVSS33 P I O Ground 116 USBVDD33 P USB Power supply 3 3V 117 USBDP B USB D 118 USBDM B USB D 119 USBVSS33 P USB Ground 3 3V 120 PLL3VSS12 P PLL3 Ground 1 2V 121 PLL3VDD12 P ...

Page 39: ...BX8804 8805 18 21 20 PACKAGE DIMENSIONS ...

Page 40: ...BX8804 8805 19 21 20 1 BX8805 PACKAGE DIMENSION 20 1 1 128 PIN Figure 28 BX8805 PACKAGE DIMENSION 128 TQFP 1414 ...

Page 41: ...BX8804 8805 20 21 21 ELECTRICAL CHARACTERISTICS ...

Page 42: ... 3V 0V 1 uA IOZ Tri state Output Leakage Current 1 IOH High Level Output Current at 2 4V 2 4 V IOL Low Level Output current at 0 4V 0 4 V RPU Pull up Register 52 RPD Pull down Register 86 21 2 USB CHARACTERISTICS Table 48 USB CHARACTERISTICS Parameter Condition Min Typ Max Unit DN DP external serial resistors 18 Ω Supply Current Full Speed 8 10 mA Supply Current Syspend Mode 20 uA tRise 1 5Mbps 12...

Page 43: ... polysilicon CMOS 1 transistor memory cell 2 Bank 524 288 word 16 bit configuration Single 3 3V power supply 0 3V tolerance Input LVTTL compatible Output LVTTL compatible Refresh 4096 cycles 64ms Programmable data transfer mode CAS Latency 1 2 3 Burst Length 1 2 4 8 Full Page Data scramble sequential interleave CBR auto refresh Self refresh capability Packages 50 pin 400mil plastic TSOP Type II TS...

Page 44: ...Column Address Strobe NC No Connection WE Write Enable Note The same power supply voltage must be provided to every VCC pin and VCCQ pin The same GND voltage level must be provided to every VSS pin and VSSQ pin 50 Pin Plastic TSOP II K Type 24 19 20 21 22 23 14 15 16 17 18 7 44 37 36 35 34 33 32 31 30 29 28 27 A11 A10 VSSQ VCCQ VCCQ VSS NC UDQM NC A8 A7 A6 WE CAS RAS CS A0 A1 A2 LDQM A5 A4 CLK CKE...

Page 45: ...s Row column multiplexed Row address RA0 RA10 Column Address CA0 CA7 A11 Slects bank to be activated during row address latch time and selects bank for precharge and read write during column address latch time A11 L Bank A A11 H Bank B RAS CAS WE Functionality depends on the combination For details see the function truth table UDQM LDQM Masks the read data of two clocks later when UDQM and LDQM ar...

Page 46: ...ncy Burst Controller Internal Col Address Counter I O Controller Column Address Buffers Internal Row Address Counter Row Address Buffers 8 Row Decoder s Row Decoder s 12 Word Drivers Word Drivers 8Mb Memory Cells 8Mb Memory Cells Read Data Registe r Output Buffers Column Decoders Sense Amplifiers Input Data Registe r Input Buffers CKE CLK CS WE UDQM LDQM A11 8 12 16 16 16 16 16 8 ...

Page 47: ...W Short Circuit Output Current IOS 50 mA Operating Temperature Topr Ta 25 C RECOMMENDED OPERATIING CONDITIONS Voltages referenced to VSS 0V Parameter Symbol Min Typ Max Unit Power Supply Voltage VCC VCCQ 3 0 3 3 3 6 V Input High Voltage VIH 2 0 VCC 0 2 V Input Low Voltage VIL 0 3 0 8 V PIN CAPACITANCE VBIAS 1 4V Ta 25 C f 1 MHz Parameter Symbol Min Max Unit Input Capacitance CLK CCLK 2 5 4 pF Inpu...

Page 48: ...echarge CKE VIH tCC Min 35 30 mA 3 Average Power Supply Current Clock Suspension ICC3S Both Banks Active CKE VIL tCC Min 3 3 mA 2 Average Power Supply Current Active Standby ICC3 One Bank Active CKE VIH tCC Min 40 35 mA 3 Power Supply Current Burst ICC4 Both Banks Active CKE VIH tCC Min 125 100 mA 1 2 Power Supply Current Auto Refresh ICC5 One Bank Active CKE VIH tCC Min tRC Min 80 70 mA 2 Average...

Page 49: ...ds of Power on Sequence POWER ON SEQUENCE 1 1 With inputs in NOP state turn on the power supply and start the system clock 2 After the VCC voltage has reached the specified level pause for 200µs or more with the input kept in NOP state 3 Issue the precharge all bank command 4 Apply a CBR auto refresh eight or more times 5 Enter the mode register setting command POWER ON SEQUENCE 2 1 With inputs in...

Page 50: ...rom Clock tOLZ 3 3 ns Output High Impedance Time from Clock tOHZ 8 8 ns Output Hold from Clock tOH 3 3 ns 3 Random Read or Write Cycle Time tRC 70 90 ns RAS Precharge Time tRP 20 30 ns RAS Pulse Width tRAS 48 100 000 60 100 000 ns RAS to CAS Delay Time tRCD 20 30 ns Write Recovery Time tWR 8 15 ns RAS to RAS Bank Active Delay Time tRRD 20 20 ns Refresh Time tREF 64 64 ms Power down Exit setup Time...

Page 51: ...charge Command lROH CL CL Cycle Active Command Input Time from Mode Register Set Command Input Min lMRD 2 2 Cycle Write Command Input Time from Output lOWD 2 2 Cycle Notes 1 AC measurements assume that tT 1ns 2 The reference level for timing of input signals is 1 4V 3 Output load 4 The access time is defined at 1 4V 5 If tT is longer than 1ns then the reference level for timing of input signals is...

Page 52: ...S CAS CAS Latency 2 Burst Length 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM tOH Ra Ca0 tRP tRC Qa1 Cb0 Rb Rb Ra Qa0 Qa2 Qa3 Db0 Db1 Db2 Db3 tAC tOHZ tWR Row Active Read Command Precharge Command Row Active Write Command Precharge Command tRCD ...

Page 53: ... 2 Burst Length 4 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Row Active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 High tOLZ Db tSI Qc tHI Qa tOH Ra lOWD BS BS BS BS BS Ra Cc Cb Ca tOHZ tAC tHI tSI tSI tHI tHI tSI tSI tHI tHI tSI ICCD tSI tCL tCC tCH Read Command Write Command Read Command Precharge Command ...

Page 54: ...ration 0 0 After the end of burst bank A holds the idle status 1 0 After the end of burst bank A is precharged automatically 0 1 After the end of burst bank B holds the idle status 1 1 After the end of burst bank B is precharged automatically 4 When issuing a precharge command the bank to be precharged is selected by the A10 and A11 inputs A10 A11 Operation 0 0 Bank A is precharged 0 1 Bank B is p...

Page 55: ...o avoid bus contention 2 To assert row precharge before a burst write ends wait tWR after the last write data input Input data during the precharge input cycle will be masked internally 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Read Command Read Command Write Command Write Command Precharge Command Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Cc0 Cd0 Ca0 Cb0 ...

Page 56: ...LDQM A Bank Precharge Start Row Active B Bank A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point A Bank Precharge Start A Bank Precharge Start High Ra tRRD Qa0 tWR Rb Ra Rb Ca Cb Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 Db0 Db1 Db2 Db3 Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 CAS Latency 2 CAS Latency 3 CAS Latency 1 Row Active A Bank DQ DQ UDQM LDQM UDQM LDQM ...

Page 57: ...11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb1 QBb2 QBb3 QBb4 QAc0 QAc1 QAc2 QAc3 Row Active A Bank Read Command A Bank Precharge Command A Bank Row Active B Bank Read Command B Bank Precharge Command B Bank Row Active A Bank Read Command A Bank tRRD tRC High ...

Page 58: ...10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc DAa0 DAa1 DAa2 DAa3 Row Active A Bank Write Command A Bank Precharge Command A Bank Row Active B Bank Write Command B Bank Precharge Command B Bank Row Active A Bank Write Command A Bank DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 High Precharge Command A Bank ...

Page 59: ... CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb CAc CBd CAe RAa RBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Note 1 Row Active A Bank Read Command A Bank Row Active B Bank Read Command B Bank Precharge Command A Bank Read Command A Bank Read Command A Bank Read Command B Bank IROH High ...

Page 60: ... 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Row Active A Bank Row Active B Bank Write Command A Bank Precharge Command Both Bank High RAa CAa RAa RBb RBb CBd DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 Write Command B Bank Write Command A Bank Write Command B Bank DAa2 DAa1 DAa0 CAc CBb ...

Page 61: ...CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RAa CAa RBb CBb RAc CAc RAa RBb RAc QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Row Active A Bank Read Command A Bank Precharge Command A Bank Row Active B Bank Write Command B Bank Row Active A Bank Read Command A Bank High ...

Page 62: ...Cycle CAS CAS CAS CAS Latency 2 Burst Length 4 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CAa0 CBb0 CAc0 QAa0 QAa1 QAa2 QAa3 Read Command A Bank Write Command B Bank Read Command A Bank DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 High QAc2 QAc3 ...

Page 63: ...DQM are asserted the write data in the same clock cycle is masked 4 When LDQM is set High the input output data of DQ1 DQ8 is masked 5 When UDQM is set High the input output data of DQ9 DQ16 is masked CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca Cb Cc Ra Qa0 Qa1 Qa2 Qb0 Qb1 Dc0 Note 1 Row Active Read Command CLOCK Suspension Read DQM CLOCK...

Page 64: ...EAD can be interrupted by WRITE The minimum command interval is burst length 1 cycles UDQM LDQM must be high at least 3 clocks prior to the write command CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca0 Cb0 Ra Db0 Db1 Note 1 Row Active Read Command Write Command Precharge Command tWR tRCD Db2 Db3 Da0 ...

Page 65: ... data will not output after lROH equals CAS latency 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM CAS Latency 2 CAS Latency 3 Ra Ca Note 1 Qa0 Qa1 Ra Qa2 Note 1 Qa3 Qa4 Qa5 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Note 1 Qa0 Qa1 Qa2 Qa3 Qa4 Row Active Read Command Precharge Command lROH lROH Qa5 lROH High CAS Latency 1 DQ DQ UDQM LDQM UDQM LDQM ...

Page 66: ... UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CAS Latency 2 CAS Latency 3 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Qa4 Qa0 Qa1 Qa2 Qa3 Qa4 CAS Latency 1 Read Command Cb Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Qb0 Qb1 Qb2 Qb3 Qb4 Burst Stop Command Write Command Burst Stop Command High Ca DQ DQ UDQM LDQM UDQM LDQM ...

Page 67: ... maintains the mode while CKE is low 2 To release the circuit from power down mode CKE has to be set high for longer than tPDE tSI 1CLK CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Ra Ca Ra Qa0 Qa1 Qa2 Note 2 Power down Entry Row Active Power down Exit Precharge Command Read Command Clock Suspension Exit tSI Note 1 Clock Suspension Entry tPDE tS...

Page 68: ...FEDD56V16160F 02 1 Semiconductor MSM56V16160F 26 31 Self Refresh Cycle 0 1 2 CLK CKE CS RAS CAS ADDR A11 A10 DQ WE UDQM LDQM Ra BS Ra Self Refresh Entry Self Refresh Exit Row Active tSI tRC Hi Z ...

Page 69: ...nductor MSM56V16160F 27 31 Mode Register Set Cycle Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 CLK CKE CS RAS CAS ADDR DQ WE UDQM LDQM New Command lMRD Auto Refresh tRC MRS Auto Refresh Key Ra Hi Z Hi Z High High 0 1 2 3 4 5 6 ...

Page 70: ...new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst execute Row Precharge Read L L L X X X ILLEGAL H X X X X X NOP Continue Row Active after Burst ends L H H H X X NOP Continue Row Active after Burst ends L H H L X X Term Burst Row Active L H L H BA CA A10 Term Burst start new Burst Read 3 L H L L BA CA A10 Term Burst start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 T...

Page 71: ...H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 Row Active L L L X X X ILLEGAL H X X X X X NOP Idle after tRC L H H X X X NOP Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL Refresh L L L X X X ILLEGAL H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL Mode Register Access L L X X X X ILLEGAL ABBREVIATIONS RA Row Address BA Ba...

Page 72: ...Continue power down mode H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL All Banks Idle 7 ABI L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Ne...

Page 73: ...a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof 6 The products listed in this document are intended for use in general electronics equipment for commercia...

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