Faultfinding Guide
GB 67
CDR779
8.
Transfer Characteristics
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
function generator as a sine wave generator with output level
of 1Vtt. Check this AC value with an AC mV-meter connected
to the input (pin 2) of the CD10 (7000) :
Figure 8-28
HFDET Setting
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
function generator as a sine wave generator with output level
of 500 kHz, 1Vtt. Check this AC value with an AC mV-meter :
Figure 8-29
8.3.8
Audio Part - DAC
Description
The DAC used, is the UDA1320 bit stream, continuous
calibration. I2S signals from various formats can be entered
at pins 1,2 and 3. If these signals are in phase with the
delivered system clock at pin 6, the DAC will reproduce
analog output signals at pins 14 and 16. 0dB level is
0.85Vrms. These analog signals are at 1.65Vdc level.
The DAC has features which can be checked on the input
pins. Mute will switch off the analog signals. De-emphasis is
not used, since this is done in the decoder. Attenuation of -
12dB is not used because this is also done in the decoder.
I2S
I2S is a kind of digital audio format, consisting out of 3 lines :
CLOCK, WORDSELECT and DATA.
WORD-SELECT
Word select (WS) indicates whether the data-sample is from
the left or the right audio-channel. It has the same frequency
as the sample rate of the digital audio signal. This can be 32,
44.1 or 48kHz. Normal polarity is low for a left sample and
high for a right sample. So within the low state of the WS-line
the data bits for the left channel are transferred, and within
the high state the data bits of the right channel are
transferred.
CLOCK
The CLOCK signal (CLK) indicates when DataTips must be
set, and when DataTips must be read. The frequency
depends on the speed of the I2S-bus, but is always a factor
of the frequency of the WS-signal. It can be 48x, 64x, 96,
128x... .In our case it is 48x the sample rate frequency =
2.1168MHz. The signal is in phase with the WS-signal.
Transition of the WS always happens on a falling edge of the
CLK.
DATA
DATA contains all data-bits. Data bits are set by the
transmitting device, and read by the receiving device. The
position of the DATA-bits within the WS-signal is very
important. There are several formats for this. In our case we
always use Philips I2S format, no Japanese or Sony format.
The number of data-bits per channel depends on the used
devices.
Timing of the I2S-bus, in case of Philips I2S is shown in the
next figure :
Figure 8-30
S1 and S2 “low”
S1 and S2 “high”
Frequencies
Input V
AC
Pin 2 at 7000
Input V
AC
Pin 2 at 7000
300 Hz
200mV
< 100mV
±
20%
200mV
< 100mV
±
20%
10 kHz
200mV
295mV
±
20%
200mV
330mV
±
20%
100 kHz
200mV
310 mV
±
20%
200mV
330 mV
±
20%
300 kHz
200mV
385 mV
±
20%
200mV
335 mV
±
20%
800 kHz
200mV
655 mV
±
20%
200mV
485 mV
±
20%
1.5 MHz
200mV
1.1V
±
20%
200mV
760 mV
±
20%
3MHz
200mV
1.1V
±
20%
200mV
1.1V
±
20%
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Location
Voltage DC
Voltage AC
No HF
HF
F190
4.8V
±
20%
4.8V
±
20%
175mV
±
20%
F192
< 100mV
1.1V
±
20%
-
F206
4.9V
±
20%
150mV
±
20%
-
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MSB
MSB
LEFT SAMPLE
RIGHT SAMPLE
WS
CLK
DATA
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