Philips AZ9003/19, Service Manual

Page: 16 / 22

3-8 3-8
CS 46 673
SAA7324H
CD10
SM5903BF
NPC TDA1300T
HF-PREAMPLIFIER
L.P.F.
H.P.F.
+
LASER
SUPPLY &
PROTECT.
R2
D1
D2
D3
D4
R1
O5
O1
O3
O4
SILD
RAB
SCL
SDA
SBSY
SFSY
YMLD
YMCLK
YMDATA
ZSENSE
SILD
RAB
SCL
SDA
SFSY (PWM_IN)
SCLK
WCLK
DATA
SCLI
WCLI
SDI
O6
Hf
D1
D2
D3
D4
D5
RFE HFIN
RESET
R2
D1
D2
D3
R1
LDon Vddl LDON
H=Laser on
A0...A10, D0...D3
CAS, RAS, WE, OE
MI
+2.7
DISC
Laser
diode
PHOTO DIODE
ARRAY
TURNTABLE
MOTOR
TRACK
SERVO
FOCUS
SERVO
SLIDE
SERVO
D1 D2
R2 R1
D3
VAM2103/08
CD-DRIVE
Monitor
diode
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F.
L.P.F. L.P.F.
LDON
DRAM INTERFACE
A/D-CONVER
TER
SHOCK
CONTROL
CONTROLLER
INTERFACE
INPUT
INTERFACE
I/O
EXTENSION
OUTPUT
INTERFACE
YFLAG
(FROM
CD10)
YMLD
YMCLK
YMDATA
ZSENSE
YSCK
YLRCK
YSRDATA
ZSCK
ZLRCK
ZSRDATA
SBSY
SERIAL
INTERFACE
SERIAL
LOOPBACK
µ
P
INTERFACE
LCD
DECODER ENCODER
CONTROL PART
ATTENUATOR INPUT BUFFER
EBU
INTERFACE
RAM
ADDRESS.
SUBCODE
PROCESS.
MOTOR
CONTROL
OUTPUT
STAGES
ERROR
CORRECT.
FRONT END TIMING
DIGITAL PLL
SRAM
EFM
DEMOD.
Vref
KILL
PRE-PROC.
FUNCTION
CONTROL
BITSTREAM
DAC
VERSATILE
INTERFACE
AUDIO
PROCESS.
PEAK
DET.
P TMP86CH29
LF
LCD DRIVER
CLOCK GEN.
& TIMING
MEMBRANE
KEYBOARD
16bit TIMER
COUNTER
ALU
ROM RAM
4MHz
I/O PORTS
RCI, RCO
Lo
LO LD
+2.7
SL
(PWM signal)
SL FO RA
FO
(PWM signal)
RA
(PWM signal)
SLIDE_IN
FOCUS_IN
DM
±
Sldm
±
Focus
±
TRACK_IN
+1.4 +2.7
MPC17A50VM
SERVO DRIVER
SAWTOOTH
OSCILLATOR
OSCILLATOR
LOW VOLTAGE
DETECTOR
2xVOLTAGE
DOUBLER
DM_IN
VLG VR CLK
DM_PWM
(FROM
µ
P)
CLsaw VG VLG VR
CLsaw
+2.7
VG
+A
Track
±
L.P.F.
L.P.F.
L.P.F.
FLEX PCB
DC-in socket
+
ACCU or
BATTERY
+
charge
ACCU
DETECT.
SUPPLY/CHARGE CIRCUIT
BEEP
CHG_ON
TEMP
DC_IN
MUTE
HP_ON
A
CCU_IN
CHG_DET
BA
T_LEVEL
DM_PWM
(T
O SER
V
O
)
PORES
(T
O CD10)
NPC_RESET
(T
O NPC)
DBB_ON
DBB_STEP
DC/DC
UP/DOWN
CONVERTER
NPC_RESET
(FROM
µ
P)
RESET
PORES
(FROM
µ
P)
RESET
ACCU_IN
(TO
µ
P)
TEMP
(TO
µ
P)
DM_PWM
(FROM
µ
P)
+A
+DC
RECH. BATT.
MEASURING
PART
CHARGE
CONTROL
+1.25
+3
+3 +1.25
+2.7
FROM/TO SUPPLY/
CHARGE CIRCUIT
TO HEADPHONE AMP.
DRAM
RC
(FROM/TO RC-SOCKET)
RC-CIRCUIT
1)
CLsaw VG VLG VR
H-BRIDGE
MOTOR DRIVER 4
H-BRIDGE
MOTOR DRIVER 3
H-BRIDGE
MOTOR DRIVER 1
CLsaw VG VLG VR
CLsaw VG VLG VR
H-BRIDGE
MOTOR DRIVER 2
tu
rntable
8.4MHz
L.P.F.
1)
not on all versions
TEMP.
DETECT.
VDDL
VDD VDD
VDD
+2.7
+UP
+2.7
VCC
+2.7
HF-GAIN
CHG_ON
(FROM
µ
P)
DC_IN
(TO
µ
P)
HEADPHONE&
RC-SOCKET
RC
(FROM/TO
RC-CIRCUIT)
YFLAG
(TO NPC)
TA2120FN
HEADPHONE AMP.
VCC
+A
VOLUME
A (RIGHT)
B (LEFT)
ADD OUT
BEEP
BIAS
DBB
CONT.
DBB
SW.
POW.
SW.
MUTE
SW.
Vref
BEEP
(FROM
µ
P)
DBB_ON
(FROM
µ
P)
DBB_STEP
(FROM
µ
P)
HP_ON
(FROM
µ
P)
MUTE
(FROM
µ
P)
IN A
IN B
DBB NF
DBB OUT
BIAS IN
BIAS
CHG_DET
(TO
µ
P)
BATT_LEVEL
(TO
µ
P)
3V
0
-3V
2,5V
0
-2,5V
eye-pattern signal
> 800 mVpp
TB=0.5
µ
s
1
during focus search
TB=0.1s
9
12
10
11
3V
0
servo in or disc motor cw
not moving
servo out or disc motor ccw
servo out or disc motor cw
not moving
servo in or disc motor ccw
16
14
13
15
DATA
WCLK
left channel
MSB
LSB
MSB
LSB
right channel
SCLK
TRANSFER OF AUDIO SAMPLES VIA SERIAL INTERFACE OF CD10 AND NPC CD10
→
NPC
NPC
→
CD10
2
3
4
5
6
7
1
14
16
15
2-4
5-7
13
9
11
10 12
BLOCKDIAGRAM