Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 109
A02U AA
9.
RGB Control Processing
•
The RGB control circuit of the DOP contains two sets of
input signals:
–
The first RGB input (RGB), 10 bits wide, is intended for
the normal video signals coming from the BEF part.
The "RGB" signals will first enter a contrast control
stage, followed by a brightness control stage, both
influenced by a combination of user control, Beam
Current Limiter and Peak White Limiter, followed by a
soft clipper stage. Then the signal will be applied to the
blender stage. The blender input signal will be used as
an input for the peak white limiting system.
–
The second RGB input (GFX), 4 bits wide, is intended
for OSD and Teletext signals. The switching between
the internal signal and the OSD signal is realized via a
blending function. The "GFX" input signals will be re-
formatted to 10 bits wide internally before entering the
Beam Current Control brightness correction stage,
followed by the hard clip stage. Then the signal will also
be applied to the blender stage.
•
The blender combines the two input data streams into one
stream. A third data stream controls this blender.
•
The next block is the "Drive Adjust" part. It contains a
Picture Tube Biasing system, a Beam Current Control, and
Peak White Limiting part.
In order to enhance the spatial bandwidth of the CRT display,
Scan Velocity Modulation (SCAVEM) is implemented on the
CRT-panel.
Figure 9-17 ADOC RGB control block diagram
Synchronization and Deflection Processing
•
Horizontal synchronization and drive circuit. The
horizontal drive signal is obtained from an internal
oscillator, which runs at a fixed frequency of 54 MHz. This
oscillator is synchronized to the incoming horizontal H_D
pulse by means of a digital PLL. The horizontal drive signal
is generated by a second control loop, which compares the
phase of the reference signal (applied from the internal
DTO) to the horizontal flyback pulse HFB.
•
Vertical deflection and drive circuit. The drive signals for
the vertical and E/W deflection circuits are generated by a
vertical divider, which derives its reference signal from the
Horizontal Time base Generator. The incoming V_D pulse,
generated by the input processor or the Feature Box,
synchronizes this divider. The vertical drive output is
realized by a differential voltage, which is generated by
SDACs. The outputs must be DC-coupled to the vertical
output stage (TDA8177, item 7620 on the LSP).
See also figure "DOP block diagram"
9.6
Synchronization
9.6.1
Sync Flow
The CVBS signal on the SCART1/AV1 connector (CVBS-
SC1_AV1-IN system signal path; designated as EXT 1 CVBS)
is used to provide synchronization for the EXT1 RGB input.
Besides providing synchronization for RGB source, EXT1
CVBS is also required for SCART2/AV2 CVBS output.
Figure 9-18 Sync flow block diagram
For 1fH CVI input, synchronization is derived from sync-on-Y.
For the 2fH CVI input, synchronization signal is derived from
sync-on-Y input or the H_SYNC/V_SYNC.
In case of VGA input, synchronization signal is taken from
H_SYNC and V_SYNC inputs
In case of HDMI input, synchronization signal is taken from
H_HDMI and V_HDMI outputs from the HDMI panellink
receiver.
9.7
Audio
9.7.1
Introduction
Sound IF processing, audio source selection, and audio
analog-digital signal conversions are done in the MPIF IC. SIF
demodulation, sound system auto-detection, audio base-band,
and headphone processing is done in the ADOC IC. Therefore,
the ADOC contains a digital TV sound processor for analog
and digital multi-channel sound systems in TV sets. By
hardware programming, several applications can be scaled.
The sound processing of the SALSA system can be split into
three parts:
•
Initial source selection and analog to digital conversion
performed by MPIF.
•
Demodulator and Decoder (DEMDEC) performed by the
ADOC.
•
Back End Features (BEF) performed by the ADOC.
9.7.2
MPIF Sound part
The (main) Tuner receives an RF signal and converts it to IF.
Via the appropriate SAW filters, the SIF signal is delivered to
the QSS mixer stage of the MPIF IC and if channels according
to standard L/L' are received also to the AM demodulator. The
Quasi Split Sound demodulation generates the SSIF or
intercarrier signal. By the SSIF switch, it is possible to choose
between the internally derived intercarrier and an external
second SIF (e.g. from a PIP front end or 10.7 MHz radio). The
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071003
DRIVE
ADJUST
CDAC
BLENDER
CONTROL
ADC
LEAKAGE
COMPASATOR
7310
7330
R-CRT
G-CRT
B-CRT
CUTOFF
ROUTP
GOUTP
BOUTP
DRIVE
ADJUST
CDAC
RGB
CUTOFF
RGB
GAIN
BLENDER
CONTROL
ADC
LEAKAGE
COMPASATOR
FIXED
BEAM
CURRENT
SWITCH
OFF
GFX
ROUTP
BOUTP
IBC
IBCRANGE
ADOC RGB
7300-H
R
G
B
7320
41
25
24
23
21
VDDE
FROM
B6
B11
CDAC2
-
VDDA
CDAC1
-
VDDA
Y-SCAVEM
BLEND
E
R
BLANKIN
G
SCAVEM
SVMP
7346
7356
TILT
B8
7304
R
G
B
FBL
PR / R
Y / G
PB / B
Hsync
Vsync
NC
FBL/Hsync1
FBL/Hsync2
Vsync1
Vsync2
Clamp1
Clamp2
HV sync Clamp1
HV sync Clamp2
G1/Y1/Y1
B1/Pb1/U1
R1/Pr1/V1
G2/Y2/Y2
B2/Pb2/U2
R2/Pr2/V2
CVBS
CVBS1
DLink1
DLink2
DLink3
SCART 1
2f
H
CVI
or VGA
MPIF IC
ADOC IC
SBL
SBL
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