Block Diagrams, Test Point Overviews, and Waveforms
EN 25
LGE PDP 2K6
6.
6.
Block Diagrams, Test Point Overviews, and Waveforms
6.1
Block Diagram PDP Module
Figure 6-1 Block Diagram
7.
Circuit Diagrams and PWB Layouts
Not applicable
ත
Applied Volt
a
ge level i
s
s
pecified
a
t the time when F
u
ll-White p
a
ttern i
s
di
s
pl
a
yed on the p
a
nel.
Color PDP
1024 X 76
8
pixel
s
Addre
ss
Driver
r
e
vi
r
D
n
a
c
S
r
e
vi
r
d
ni
a
t
s
us
n
o
m
m
o
C
Vcc (5V)
Di
s
pl
a
y d
a
t
a
, Driver timing
Memory
Controller
Driver
Timing
Controller
Inp
u
t
Interf
a
ce
Controller
V
a
(60+ 1V)
V
s
(175V~190V)
Controller
(Extern
a
l Power)
RA+
RA-
RB+
RD+
RD-
RB-
RC+
RC-
RE+
RE-
RCLK-
RCLK+
(LVD
S
inp
u
t)
I2C
G_16
3
90_079.ep
s
3
10
8
06
