EN 88
QFU1.2E LA
10.
Circuit Diagrams and PWB Layouts
2014-Jan-10
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div. table
10-1-30
B06D, Ethernet
19370_156_130227.eps
130227
Ethernet
B06D
B06D
2012-11-22
4
3104 313 6612
Ethernet
TX+
TX-
RX+
RX-
VIA
VDDH_REG
VDDIO_REG
TRXP0
TRXN0
TRXP1
TRXN1
CLK_RMII
CRS_DV
LX
RXD0
RXD1
RX_ER
TX_EN
TXD0
XTLI
XTLO
CLK_25M
RST
RBBIAS
RES0
RES1
AVDDL
VIA
MDIO
INT
NC
MDC
GND_H
S
TXD1
LED_ACT
LED_RES
LED_10_100
DVDDL
VDD
33
AVDD
33
16V
CDA5C16GTH
6EF2-
3
RE
S
3
6
2EFL
RE
S
VDDH-2V5
VDDH-2V5
15p
2EFC
22p
2EF9
10
u
10
u
2EF2
2EF
3
100n
FEF8
FEFE
FEFD
1
u
0
2EFF
VDDH-2V5
+3V3-STANDBY
IEF2
AVDDL-1V1
IEF3
1%
1K5
3EF3
8
2EF
8
100n
1E00
5450-327-194-H3
1
2
3
4
5
6
7
1M0
3
EFY
100n
2EFA
FEF7
3EFN
FEFA
5EF4
10K
30R
10n
2EFT
3EFM
10K
3EFU
10K
8
3EFL
10K
RE
S
16V
CDA5C16GTH
6EF2-1
1
FEF6
+3V3-LAN
FEF9
RE
S
15p
2EFK
100n
2EFZ
2EF
S
10n
FEF0
3EFS
10K
RES
30R
5EF0
15p
RE
S
2EFN
100n
2EF7
22p
2EFB
FEF3
100n
2EFH
25M
1EF0
22
u
2EFV
10K
3EFR
16V
4
5
2EFP
100n
10K
3
EF4
RE
S
6EF2-4
CDA5C16GTH
1%
2K37
3EF2
5EF5
30R
3EFH
10K
RE
S
2EF0
1
u
0
15p
2EFM
IEF1
FEF4
3EFP
10K
FEFC
22R
3EF5
2EFU
100n
VDD33-PHY
3EFJ
10K
100n
2EF1
4
u
7
5EF1
50
5
4
2EFJ
100n
56
57
58
4
3
44
45
46
47
4
8
49
34
35
32
3
8
27
42
51
52
53
54
55
26
31
1
29
28
25
10
13
9
12
22
2
40
39
15
16
18
19
36
37
7
11
17
23
33
30
38
41
20
24
21
7EF0
AR8030-AL1A-R
14
6
6
1
DEF0
4
7EF1-1
PUMH2
2
7EF1-2
PUMH2
5
3
VDD33-PHY
VDD33-PHY
10K
3EFT
16V
RE
S
6EF2-2
2
7
RE
S
CDA5C16GTH
100n
2EF5
FEFB
FEF2
FEF1
30R
5EF6
VDD33-PHY
VDD33-PHY
FEF5
2EFG
1
u
0
2EF6
100n
TXP
TXN
RXP
RXN
IRQ-WOLANn
EN-RXC
LED-ACT
RESET-ETHERNETn
RES0
RES1
LED-RES
LED-ACT
EN-RXD0
EN-RXD1
EN-RXEN
RX-ER
LED-RES
EN-RXD0
EN-RXD1
RX-ER
TXN
RXN
TXP
RXP
EN-TXD0
EN-TXD1
EN-TXEN
EN-MDC
EN-MDIO
RES0
RES1
CLK-RMII
CLK-RMII
EN-TXC
EN-RXEN