EN 62
QFU1.2E LA
10.
Circuit Diagrams and PWB Layouts
2014-Jan-10
back to
div. table
10-1-4
B01D, USB internal
19370_130_130227.eps
130227
USB internal
B01D
B01D
2012-11-22
4
3104 313 6612
USB internal
NC
GND
GND
HS
VIN
EN
VIA
VOUT
BP|ADJ
VCC_A_
3
VCC_D
XIN
XOUT
DD1-
DD1+
OVR1
DD2-
VIA3
VIA4
VCC
VCC_A_1
VCC_A_2
DD2+
OVR2
DD3-
DD3+
OVR3
DD4-
DD4+
OVR4
VREG
RESET
SELFPWR
GANG
RREF
GND_H
S
TEST|SCL
SDA
D-
D+
VIA1
VIA2
GND_H
S
VOUT
FB
VIA
VAUX
L
UVLO
EN
PS
VIN
GND
PGND
reserved
RE
S
2EH
S
22
u
RE
S
3
EHP
1
%
120K
100n
2EM2
+5V
+3V3-LAN
3EM3
10K
FEH8
RES
9EHE-3
9EH8-1
FEH4
RES
RES
9EHE-1
6
7
8
IEH4
1
2
3
4
5
9EM2
1C31
A1253WRA
+3V5-STANDBY
2EM4
100n
IEH2
680R
RES 5EH0
4u7
IEH0
3EM4
2EHW
10n
47K
3EHV
RE
S
100n
2EHP
7
10
1
2
3
4
RES
RT9187GSP
7EH2
5
8
6
9
10
u
2EHL
9EM
3
RE
S
3
EHT
22K
3
EHJ
FEH1
+3V3
+3V3
100K
3EM6
10K
FEH3
IEHJ
IEH3
IEH6
+3V3-WIFI
IEM1
IEM2
+3V3
RES
2EHV
100n
+3V3
3
EM1
1M0
FEH2
2EM
3
14
21
30
31
32
33
28
10
11
100n
20
19
17
8
26
22
18
27
5
9
12
13
15
16
1
2
23
29
25
24
3
4
6
7
22
u
2EHT
7EM1
CY7C65632-28LTXCT
RE
S
3
EM5
100K
IEH5
IEH1
FEH7
2EHY
100
u
6.
3
V
RE
S
100n
2EHJ
RES
9EHE-2
RE
S
33
0K
3
EH
S
3EHU
22K
9EH8-4
RES
9EHE-4
9EM1
RES
1
%
+3V3
RE
S
3
EHR
22K
2EHN
100n
RES
+3V3
2EM5
12M
1EM0
100n
22
u
2EHR
RE
S
cEH0
RES
FEH6
3EHN
10K
10K
3EM8
10K
3EM7
18p
2EM1
100n
2EM7
2EM6
100n
3
4
5
6
7
RE
S
2EHU
1n0
1C30
A1253WRA
1
2
18p
FEH9
2EM0
+3V3
1
%
10K
3
EM0
7EHJ
BC847BW
+3V5-STANDBY
1M0
3
EHY
2
2EH9
47n
9
11
3
4
8
7
1
12
13
5
7EH4
TPS61200DRCG4
0
1
6
2EHM
10
u
RES
FEH5
RES
+3V3-LAN
+3V3
9EH8-2
RES 9EH8-3
1
%
33
K
3
EHW
3EM9
10K
USB-WIFI-DP
ENABLE-WOLAN
+3V3-LAN
M
D
-
I
F
I
W
-
B
S
U
M
D
-
1
B
S
U
P
D
-
I
F
I
W
-
B
S
U
P
D
-
1
B
S
U
USB-WIFI-DM
IRQ-WOLANn
USB-CAM-DM
USB-CAM-DP
USB1-DM
USB1-DP
RESET-FUSION-OUTn
USB-CAM-DM
USB-CAM-DP
USB-WIFI-DM
USB-WIFI-DP