EN 80
10.
Circuit Diagrams and PWB Layouts
10-1-11
B03C, UMAC 1 DDR3
19210_015_120424.eps
120424
UMAC 1 DDR3
B03C
B03C
2011-12-22
3
8204 000 9237
UMAC 1 DDR3
7
15
8
9
10
11
12
13
14
VREFDQ
VREFCA
ZQ
BA0
BA1
BA2
RAS
DQSL
ODT
2
1
0
DMU
DML
RESET
WE
CS
6
5
NC
4
3
CK
CK
CKE
7
BC
AP
VSS
VSSQ
VDD
VDDQ
0
1
2
3
4
5
6
DQSU
DQU
0
1
2
3
4
5
6
7
DQL
A
CAS
DQSU
DQSL
7
15
8
9
10
11
12
13
14
VREFDQ
VREFCA
ZQ
BA0
BA1
BA2
RAS
DQSL
ODT
2
1
0
DMU
DML
RESET
WE
CS
6
5
NC
4
3
CK
CK
CKE
7
BC
AP
VSS
VSSQ
VDD
VDDQ
0
1
2
3
4
5
6
DQSU
DQU
0
1
2
3
4
5
6
7
DQL
A
CAS
DQSU
DQSL
100R
3J1G
100R
3J1F
2J17
100n
100n
2J1R
DB97
DB90
100n
2J1N
100n
2J1M
DB98
10
u
2J24
3J2N
100R
3J2M
100R
DBA1
DBA2
DBA8
+1V5-M1
3
J15
1K0
DB91
10
u
DB66
2J22
DB39
DB65
DB44
DB43
DB42
100R
3J2K
DB31
FJ08
DBA6
DB45
DBA5
DB48
2J1T
100n
DB34
DB32
DB96
DB94
DB95
DB93
DB35
3J2R
100R
100n
2J16
3J1V
100R
3J2D
100R
100R
3J1Y
DB56
DB57
100R
3J1L
3J2L
DBA7
100R
DB40
2J1F
+1V5-M1
10n
100n
2J1Z
100R
3J2P
2J
8
6
10n
3J26
100R
100n
2J20
DB55
DB54
100n
2J1U
3
J11
1K0
100n
2J1
S
DBA3
DB49
DB01
DB99
2J1J
10n
10n
2J1K
100R
3J2G
100R
3J2F
3J1E
100R
100n
2J15
100R
3J28
100R
3J1K
DB38
2J1V
100n
100R
3J2Q
2J1P
100n
3
J10
240R
DB36
100R
3J2B
DBA4
3J1J
100R
DB33
3J2S
100R
100R
3J1P
3J1N
100R
3J1M
100R
DB92
75R
3
J16
3J1H
100R
100R
3J1B
10n
2J1G
2J1C
DB60
+1V5-M1
10n
10n
2J12
RES
DB52
2J1Q
100n
G1
G9
L3
L8
J
8
M1
M9
P1
B1
B9
D1
D
8
E2
E
8
F9
M8
H1
A9
P9
T1
T9
B
3
E1
G
8
J2
R9
A1
A
8
C1
C9
D2
E9
F1
H2
H9
K1
J3
T2
B2
D9
G7
K2
K
8
N1
N9
R1
C3
C8
C2
A7
A2
B8
A3
J1
J9
L1
L9
F8
H3
H8
G2
H7
F3
G3
C7
B7
D7
M3
K3
J7
K9
K7
L2
E7
D3
E3
F7
F2
M7
P3
N2
P8
P2
R8
R2
T8
R3
M2
N8
N3
P7
L7
R7
N7
T3
T7
7J02
H5TQ2G63BFR-PBC
100R
3J1C
2J1W
100n
FJ09
2J1D
10n
100n
2J14
B9
D1
D
8
E2
E
8
F9
G1
G9
L3
L8
T1
T9
B
3
E1
G
8
J2
J
8
M1
M9
P1
B1
C9
D2
E9
F1
H2
H9
M8
H1
A9
P9
G7
K2
K
8
N1
N9
R1
R9
A1
A
8
C1
B8
A3
J1
J9
L1
L9
K1
J3
T2
B2
D9
H7
F3
G3
C7
B7
D7
C3
C8
C2
A7
A2
L2
E7
D3
E3
F7
F2
F8
H3
H8
G2
R8
R2
T8
R3
M2
N8
M3
K3
J7
K9
K7
P7
L7
R7
N7
T3
T7
M7
P3
N2
P8
P2
7J01
H5TQ2G63BFR-PBC
N3
DB58
DB59
DB50
+1V5-M1
2J21
100n
2J
8
1
10n
1K0
3
J12
3J2E
100R
DB62
DB41
2J
8
2
10n
100n
2J19
2J1L
100n
240R
3
J1
3
3J19
100R
DB53
+1V5-M1
2J25
10
u
100R
3J20
3J1W
100R
+1V5-M1
100R
3J18
2J1A
100n
DB63
DB64
100R
3J2C
2J1E
10n
+1V5-M1
2J1
8
100n
3J1R
100R
3J2J
100R
10n
2J
8
7
DB51
100n
2J1B
10n
2J
8
5
100R
3J1U
2J
8
9
10n
3J1D
100R
3
J17
75R
10n
2J
88
3J1S
100R
2J
83
10n
+1V5-M1
100R
100R
3J1Z
3J1A
3J2H
100R
3J29
100R
100R
3J24
100R
3J23
100R
3J27
10n
2J
8
4
1K0
3
J14
2J1H
10n
100R
3J2T
100R
+1V5-M1
3J22
2J27
47
u
16V
+1V5-M1
3J21
100R
3J25
100R
3J2A
100R
100R
3J1T
M1-MD17
M1-MD18
M1-MD19
M1-MD20
M1-DQM1
M1-MD26
M1-MD25
M1-MD24
M1-MD29
M1-MD21
M1-MD22
M1-MD23
M1-MD16
M1-MD0
M1-MD7
M1-MD2
M1-MA15
M1-MA15
M1-MD28
M1-MD31
M1-MD30
M1-MD27
M1-DQS#1
M1-DQS0
M1-DQS#0
M1-MD1
M1-MD4
M1-MD3
M1-MD6
M1-MD5
M1-MD15
M1-MD12
M1-MD11
M1-MD8
M1-MD9
M1-MD10
M1-MD13
M1-DQS1
M1-CS#
M1-ODT
M1-CKE
M1-RESET#
M1-MD14
M1-MA8
M1-MA9
M1-MA10
M1-MA11
M1-MA12
M1-MA13
M1-MA14
M1-MA15
M1-BA0
M1-BA1
M1-BA2
M1-RAS#
M1-CAS#
M1-WE#
M1-MCLK0
M1-MCLK0#
M1-MA0
M1-MA1
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-RESET#
DDR-MVREF12
M1-WE#
M1-RAS#
M1-DQM2
M1-DQM3
DDR-MVREF12
M1-CAS#
M1-MCLK0
M1-CKE
M1-MCLK0#
M1-CS#
M1-DQS3
M1-DQS#3
M1-DQS2
M1-DQS#2
M1-MA14
M1-ODT
M1-MA10
M1-MA11
M1-MA12
M1-MA13
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-MA8
M1-MA9
M1-BA0
M1-BA1
M1-BA2
M1-ODT
M1-RESET#
DDR-MVREF11
M1-WE#
M1-RAS#
M1-DQM0
DDR-MVREF11
M1-MA0
M1-MA1
M1-MA0
M1-MA1
M1-MA10
M1-MA11
M1-MA12
M1-MA13
M1-MA14
M1-MA2
M1-MA3
M1-MA4
M1-MA5
M1-MA6
M1-MA7
M1-MA8
M1-MA9
M1-BA0
M1-BA1
M1-BA2
M1-CAS#
M1-MCLK0
M1-CKE
M1-MCLK0#
M1-CS#