Circuit Diagrams and PWB Layouts
EN 109
Q549.2E LA
10.
2009-May-08
SSB: PNX5100 - PCI
C
7
8
9
10
11
12
13
0
CLK
INTA
0
1
2
3
5
6
AD
CBE
SEL
XIO
GNTB
GNTA
GNT
REQB
REQA
REQ
SERR
PERR
IDSEL
DEVSEL
STOP
TRDY
IRDY
FRAME
PAR
3
2
1
0
3
PLL_OUT
4
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
AD25
ACK
2
1
6
5
3
8
is prohibited without the written consent of the copyright
1
8
G
B
5
I
F
B
C
E
E
9
1
A
D
IC50 C5
C
10
10
3CFK-1 B5
owner.
D
7
E
3CFN B5
J
3CFL-1 B5
6
A
3CF1 C5
7
3
11
6
E
4
12
4
2
8
7C00-2 A3
1
4
C
A
3
1
D
13
11
IC51 C5
A
5
7
12
All rights reserved. Reproduction in whole or in parts
J
I
2
6
H
4
3CFL-3 B5
D
3CFL-2 B5
8
5
3CFK-3 B5
C
B
B
H
G
F
13
3CFK-2 B5
2
3
9
7
2
PNX5100 : PCI
+3V3
Maelegheer Ingrid
2008-10-10
3
A3
PCI PNX5100
TV543 R2 LDIPNX
8204 000 8928
CHECK
DATE
NAME
2
SUPERS.
CLASS_NO
E
M
A
N
T
E
S
N
H
C
9
7
ROYAL PHILIPS ELECTRONICS N.V. 2008
2008-11-21
130
1
8
RES 3CFK-1
100R
3
6
RES
100R
3CFK-3
3
6
RES 3CFL-3
100R
IC50
10K
3CF1
3CFK-2
100R
2
7
AC6
AF7
M2
M3
M4
N1
RES
M1
V1
W3
W1
AD6
AC7
AD7
W2
V4
V2
H1
AD5
AC5
AF4
L3
V3
U2
AE6
AF6
AE7
L4
N4
AF3
N3
N2
AE3
AF2
AB2
AB1
AA4
AA3
AE5
T3
AD4
T2
T1
R4
R3
R2
P4
P3
P2
P1
AE4
AA2
AA1
Y4
Y3
Y2
Y1
W4
U1
T4
Φ
PCI_XIO
PNX5100E
7C00-2
AF5
IC51
3CFL-2 2
7
+3V3
RES
100R
10K
3CFN
1
8
RES
100R
3CFL-1
PCI-CBE0
PCI-CBE1
PCI-CBE2
PCI-CBE3
PCI-CLK-PNX5100
PCI-DEVSEL
PCI-FRAME
PCI-AD25
PCI-IRDY
PCI-PAR
PCI-PERR
PCI-SERR
PCI-STOP
PCI-TRDY
PCI-AD0
PCI-AD1
PCI-AD10
PCI-AD11
PCI-AD12
PCI-AD13
PCI-AD14
PCI-AD15
PCI-AD16
PCI-AD17
PCI-AD18
PCI-AD19
PCI-AD2
PCI-AD20
PCI-AD21
PCI-AD22
PCI-AD23
PCI-AD24
PCI-AD25
PCI-AD26
PCI-AD27
PCI-AD28
PCI-AD29
PCI-AD3
PCI-AD30
PCI-AD31
PCI-AD4
PCI-AD5
PCI-AD6
PCI-AD7
PCI-AD8
PCI-AD9
1
83
10_524_090
3
02
.ep
s
090
3
02