Philips 32PFL3505D/F7, Service Manual

Page: 52 / 108

9-16
4. Digital Signal Process Block Diagram
LV
D
S
T
X
AD23 AD24 AE23 AF23 AF22 AE22 AD21 AD22 AF24 AE24
W25 W23
Y24 Y23 Y22
TP
POL
CPV
OE
STV
CN3902
48 47 46 45 44 43 38 37 36 35 34 33 42 41 63 64 30 31 32
IC3901
(TINING CONTR
OLLER)
8 7
10
9
12 11 16 15 14 13
DA
T
A
PR
OCESSING
FRC LINE B
UFFER
GAMMA CORRECT
OR
LV
D
S
RX
LV
D
S
OUTPUT
DA
T
A
INPUT LA
TCH
DIGIT
AL MAIN CB
A UNIT
IC3301
(DIGIT
AL SIGNAL PR
OCESS)
LCD MODULE ASSEMBL
Y
DIGIT
A
L
SIGNAL PR
OCESS
A/D CONVER
TER
S-VIDEO-Y
-IN
SW
V1 U2 U1
S-VIDEO-C-IN
U3
VIDEO-IN
V3
COM-VIDEO-Pr-IN COM-VIDEO-Pb-IN COM-VIDEO-Y
-IN
AA3
IF-A
GC
HDMI-IN1 HDMI-IN2
JK3701
TMDS-D0(+) TMDS-D0(-) TMDS-D1(+) TMDS-D1(-) TMDS-D2(+) TMDS-D2(-) SD
A
SCL
7 9 4 6 1 3
10 12 16 15
7 9 4 6 1 3
10 12 16 15
JK3702
TMDS-D0(+) TMDS-D0(-) TMDS-D1(+) TMDS-D1(-) TMDS-D2(+) TMDS-D2(-) TMDS-CLOCK(+) TMDS-CLOCK(-) SD
A
SCL
A9 B9 C8 C9 B8 A8
B10 A10 A11 B11
A5 B5 C4 C5 B4 A4 B6 A6 A7 B7
TMDS-CLOCK(+) TMDS-CLOCK(-)
DEMODULA
T
O
R
/MPEG DECODER
AE2 AF7
A
U
DIO I/F
TO
A
U
D
IO
BLOCK DIA
GRAM
AC
L
K
AD
A
T
A1
BCLK LRCLK AD
A
T
A0
SPDIF
AD14
AD9
AD12 AD10 AD11 AC
10
D
A
T
A
(0-15)
ADDESS(0-12) IC3201
A13-15,A18, A21-23,B13-15, B17,B19-23 C15,C17-19, C23,C24,D14, D15,D17-19, D22,D23
B1,B9,C2,C8,
D1,D3,D7,D9,
F1,F9,G2,G8, H1,H3,H7,H9
M2,M3,M7,M8, N2,N3,N7,N8, P2,P3,P7,P8,R2
(DDR2 SDRAM)
HDMI I/F
HDMI-IN3
7 9 4 6 1 3
10 12 16 15
JK3704
TMDS-D0(+) TMDS-D0(-) TMDS-D1(+) TMDS-D1(-) TMDS-D2(+) TMDS-D2(-) TMDS-CLOCK(+) TMDS-CLOCK(-) SD
A
SCL
B1 B2 C1 C2 D1 D2 A1 A2 A3 B3
AU
D
IO
DECODER
DIF-OUT1 DIF-OUT2 IF-A
GC
T
O
VIDEO
BLOCK DIA
GRAM
T
O
VIDEO
BLOCK DIA
GRAM
VIDEO DECODER
AF2
S-VIDEO-SW
C6
S-VIDEO-SW
M2
A
U
DIO(R)
M1
A
U
DIO(L)
VIDEO SIGNAL
AUDIO SIGNAL
V2
LL
V1(+)
21
LL
V1(-)
20
LL
V0(+)
23
LL
V0(-)
22
LL
V2(+)
19
LL
V2(-)
18
LL
V3(+)
13
LL
V3(-)
12
LL
V4(+)
11
LL
V4(-)
10
LL
V5(+)
9
LL
V5(-)
8
LL
VCLK(+)
16
LL
VCLK(-)
15
TP
6 POL
5 CPV
4 OE1
3 STV
1
PL10.3BBLD