IC Data Sheets
8.
8.7
Diagram
B12, SII9679CNUC (IC U713)
Figure 8-9 Internal block diagram and pin configuration
19616_301.eps
Block diagram
Pinning information
1
VDD33OUT
2
VDD5V IN
3
RPWR5V
4
CBUS HPD
5
CoC GND
6
AVDD10 DoC
7
RXCN
8
RXCP
9
AVDD10
10
VDD33
11
RX0N
12
RX0P
13
RX1N
14
RX1P
15
RX2N
16
RX2P
17
AVDD10
18
FVDD10
19
VDDIO33
20
INT
21
22
23
24
G
PIO0_
C
I2
CA
G
PIO
1
_P
S
C
T
L
G
PI
O2
VDD
10
28
27
26
25
TMO
DE
NC
NC
NC
37
36
35
34
33
32
31
30
29
NC
GPIO
3
G
PI
O4
GPIO5
VDDIO
33
RE
S
ET
N
VDD10
AVDD10_
PL
L
NC
38
TX_HPD
39
AVDD10 DP
40
TXCN
54
53
52
51
50
49
48
47
46
45
44
43
42
41
HSIC STB
XTAL VDD33
TX2P
XTAL OUT
XTAL IN
HSIC DAT
NC
TX1P
TX1N
TX0N
TX0P
TX2N
XTAL GND
TXCP
55
HSIC GND
56
VDD12OUT
57
HSIC VDD33
58
H
S
IC_VDD10
VD
D
10
59
S
PI_MO
S
I
S
PI
_C
S
1
S
PI_C
S
0
S
PI
_
C
LK
60
61
62
63
D
S
CL
LP
S
BV5V
WA
K
EU
P
NC
MH
L_CD
VDD
10
C
S
CL
TD
S
DA
T
D
S
CL
VDDIO
33
S
PI_MI
S
O
D
S
D
A
64
65
66
67
68
69
70
71
72
73
74
75
76
Top View
SiI 9679
ePad (GND)
C
S
DA
SiI9679
Registers,
Configuration,
and Interrupt
Control Registers
Local I
2
C
RXCP/N
GPIO0_CI2CA
CBUS_HPD
MHL_CD
GPIO1_PSCTL
INT
VDD5V_IN
VCC33OUT
HSIC_DAT
HSIC_STB
RX0P/N
RX1P/N
RX2P/N
DDC_Rx
RPWR5V
RESETN
Video Data
Conversion
Logic
3V3
Regulator
HDMI/
MHL1, 2, 3
Receiver
1V8
Regulator
Rx HDCP
Authentication
Logic
Local I
2
C
Slave Logic
CBUS
Control
Rx DDC
Interface
Data
Tunneling
Tx DDC
Interface
SPI_MISO
SPI_MOSI
SPI_CS0
SPI_CLK
SPI Logic
HSIC PHY
DDC_Tx
GPIO2
SPI Slave
SPI Master
TX2P/N
TX1P/N
TX0P/N
TXCP/N
GPIO3
HDCP
Repeater
Logic
Tx HDCP
Encryption
Engine
HDCP
Decryption
Engine
Tx HDCP
Authentication
Logic
HDMI TMDS
Transmitter
Audio
Output
Logic
Video Data
Audio Data
WS
SCK
MCLK
SD0_SPDIF
XTALIN
XTALOUT
OTP
(SiI9394
Dongle Only)
CEC_A
CEC
Interface
(SiI9394
Dongle Only)
C
loc
k
(Co
C)
D
a
ta
(
Do
C
)
ISP
1V2 Regulator
SPI_CS1
TX_HPD
GPIO4
GPIO5
LPSB
LPSBV
WAKEUP
OSC
MCU