10.
Circuit Diagrams and PWB Layouts
SMB: Reset; Flash; SC; Bootstrap
1
888
0_524_10100
8
.ep
s
10100
8
Re
s
et; Fl
as
h;
S
C; Boot
s
tr
a
p
B11
2010-05-14
0.4
BUH NAFTA 2k10 v0.4
017G MB 4 ZW
Re
s
et; Fl
as
h;
S
C; Boot
s
tr
a
p
B11
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
NAND_ALE
NAND_CLE
NAND_RE
b
NAND_RB
b
NAND_DATA0
NAND_DATA1
NAND_DATA2
NAND_DATA
3
NAND_DATA4
NAND_DATA5
NAND_DATA6
NAND_DATA7
NAND_ALE
NAND_C
S
0
b
NAND_CLE
NAND_WE
b
NAND_RE
b
NAND_RB
b
S
F_MI
S
O
S
F_
S
CK1
S
F_C
Sb
NAND_DATA2
NAND_DATA
3
NAND_DATA4
NAND_DATA5
NAND_DATA0
NAND_DATA6
NAND_DATA1
NAND_DATA7
S
F_C
Sb
RE
S
ET
b
NAND_DATA6
NAND_DATA4
NAND_DATA5
NAND_DATA1
NAND_DATA7
NAND_DATA
3
NAND_DATA0
NAND_ALE
NAND_DATA2
NAND_C
S
0
b
_INT
S
F_
S
CK1
S
F_W
S
F_MO
S
I
RE
S
ET_TO_
S
M
NAND_C
S
0
b
_INT
NAND_WE
b
NAND_R
S
T
b
NAND_CLE
RE
S
ET_OUT
b
RE
S
ET
b
NAND_R
S
T
b
RE
S
ET_OUT
b
RE
S
ET_FROM_MCU
S
F_MO
S
I
S
F_MI
S
O
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
D
3
.
3
V
RE
S
ET_OUT
b
[25]
RE
S
ET_TO_
S
M
[24]
RE
S
ET_FROM_MCU
[19]
NAND Fl
as
h (
8
-Bit, 256 MB)
8
mA
S
ERIAL FLA
S
H (
S
ingle I/O, 2MB)
Re
s
et trigger
s
when
D
3
.
3
V < 2.9
3
V, for 200m
s
s
tr
a
p_NAND_ecc_1
3
:
8
ecc
b
it
s
2:
4 ecc
b
it
s
s
tr
a
p_NAND_ecc_0
1 :
1 ecc
b
it
0:
no ecc
s
tr
a
p_XTAL Bi
as
Ct
rl
1
[1
:0
]=
3
:
3
.0
mA
[1
:0
]=
2:
2.
4m
A
s
tr
a
p_M
IP
S
Fr
e
qu
ency
0:
M
IP
S
r
u
n
a
t 4
0
5
MH
z
1:
M
IP
S
r
u
n
a
t
3
7
8
MHz
s
tr
a
p_NAND_BK0_W
_
PROT
0:
en
ab
le
BLK0 wr
it
e
s
/
s
in
g
le
io
1:
di
sab
le
BLK0 wr
it
e
s
/m
u
lti io
s
tr
a
p_NAND_f
l
as
h_
b
oot
0:
S
er
i
a
l F
l
as
h
1: NAND Fl
as
h
s
tr
a
p_
s
y
s
te
m
b
ig
e
n
d
i
a
n
0:
Li
tt
le
1: Big
s
tr
a
p_XTAL Bi
as
Ct
rl
0
[1
:0
]=
1:
1.
8
mA
[1
:0
]=
0:
1.
2m
A
s
tr
a
p_i
2c_
s
w_l
e
vel
0:
3
.
3
V
S
wi
tc
hi
ng l
e
vel
1:
5V
S
wi
tc
hi
ng Level
8
5MHz
24mA
s
tr
a
p_d2cdi
ff
_
a
c
0 :
Di
sab
le D2CDIFF AC
1 : En
ab
le D2CDIFF AC
Progr
a
med FLA
S
H
U17-1
HY27UF0
8
2G2B-FP
Progr
a
med FLA
S
H
U17-1
HY27UF0
8
2G2B-FP
R215
0
R215
0
S
W1
S
W1
2
1
3
4
R214
1K
R214
1K
U1I
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
U1I
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
RE
S
ET
b
F6
NMI
b
N24
RE
S
ET_OUT
b
P24
R2
1
8
2.7K
R2
1
8
2.7K
R204
3
.
3
K
R204
3
.
3
K
RD9
*
2.7K
RD9
*
2.7K
1
3
2
R207
0
R207
0
U16
MX25L1655DXCI-10G
S
O16W
U16
MX25L1655DXCI-10G
S
O16W
VCC
B4
C
S
C2
S
O
D2
W
C4
GND
B
3
S
I
D
3
S
CK
B2
NC1
A1
NC2
A2
NC
3
A
3
NC4
A4
NC5
B1
NC6
C1
NC7
C
3
NC
8
D1
NC9
D4
NC10
E1
NC11
E2
NC12
E
3
NC1
3
E4
NC14
F1
NC15
F2
NC16
F
3
NC17
F4
U20
NC7
S
Z0
8
P5X
U20
NC7
S
Z0
8
P5X
1
2
4
5
3
R216
100K
R216
100K
R21
3
2K
R21
3
2K
R20
8
*
0
R20
8
*
0
C
3
25
0.1
u
F
C
3
25
0.1
u
F
Progr
a
med FLA
S
H
U16-1
MX25L1655DXCI-10G
Progr
a
med FLA
S
H
U16-1
MX25L1655DXCI-10G
R210
4.7K
R210
4.7K
U19
G692L29
3
TCFU
U19
G692L29
3
TCFU
VCC
4
V
SS
1
/MR
3
/R
S
T
2
R209
33
R209
33
U17
HY27UF0
8
2G2B-FP
<P
a
ck
a
ge>
U17
HY27UF0
8
2G2B-FP
<P
a
ck
a
ge>
CLE
D5
I/O0
H4
WP
C
3
R/B
C
8
CE
C6
RE
D4
WE
C7
V
SS
C5
VD
D
J6
VD
D
H
8
V
SS
K
3
ALE
C4
I/O1
J4
I/O2
K4
I/O
3
K5
I/O4
K6
I/O5
J7
I/O6
K7
I/O7
J
8
V
SS
K
8
RD1
6
2.7K
RD1
6
2.7K
1
3
2
RD1
4
2.7K
RD1
4
2.7K
1
3
2
RD1
5
2
.7
K
RD1
5
2
.7
K
1
3
2
TP110
TP110
RD1
8
*
2.7K
RD1
8
*
2.7K
1
3
2
S
ERIAL FLA
S
H/
S
PI
U1F
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
S
ERIAL FLA
S
H/
S
PI
U1F
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
S
PI_
S
_MI
S
O
V25
S
F_MI
S
O
W24
S
F_MO
S
I
U2
3
S
F_
S
CK
V2
3
S
F_C
Sb
V24
R217
0
R217
0
J12
HEADER 1x
3
PH2.0
J12
HEADER 1x
3
PH2.0
1
2
3
C
3
24
0.1
u
F
C
3
24
0.1
u
F
C
3
2
3
0.1
u
F
C
3
2
3
0.1
u
F
R20
3
3
.
3
K
R20
3
3
.
3
K
R24
3
1K
R24
3
1K
RD1
3
*
2.7K
RD1
3
*
2.7K
1
3
2
RD1
2
2
.7
K
RD1
2
2
.7
K
1
3
2
RD1
7
*
2.7K
RD1
7
*
2.7K
1
3
2
NAND FLA
S
H
U1H
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
NAND FLA
S
H
U1H
BCM
3
549L
BGA704_
S
KT_
S
MTBG_BCM
3
556
NAND_DATA0/EBI_DATA
8
U24
NAND_DATA1/EBI_DATA9
T26
NAND_DATA2/EBI_DATA10
T27
NAND_DATA
3
/EBI_DATA11
U26
NAND_DATA4/EBI_DATA12
U27
NAND_DATA5/EBI_DATA1
3
V26
NAND_DATA6/EBI_DATA14
V27
NAND_DATA7/EBI_DATA15
V2
8
NAND_RE
b
/POD_EBI_RD
b
T2
3
NAND_ALE/POD_EBI_D
Sb
R2
3
NAND_C
S
0
b
T24
NAND_RB
b
/D
S
_OV
S
T_CLK
U25
NAND_WE
b
/POD_EBI_WE0
b
R24
NAND_CLE/POD_EBI_TA
b
T25
RD1
0
*
2.7K
RD1
0
*
2.7K
1
3
2
C
3
22
0.1
u
F
C
3
22
0.1
u
F
RD1
1
*
2.7K
RD1
1
*
2.7K
1
3
2
R212
0
R212
0
R206
4.7K
R206
4.7K
RD
8
4.7K
RD
8
4.7K
1
3
2