Philips 19PFL5522D Service Manual Download Page 83

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Circuit Descriptions, Abbreviation List, and IC Data Sheets

EN 83

LC7.2E LB

“Block diagram video processing” shows the input and output
signals to and from the Trident Video Processor in EU
applications.

During analogue reception, a CVBS signal coming from the
analogue front-end is fed to the video processor via pin
CVBS1. During digital reception, the video signal coming from
the MPEG decoder (MOJO) is fed to the video processor via
pins FS1, PC_B, PC_G and PC_R.

The video processor also interfaces the SCART1 & 2 input,
side AV, EXT4 (HD where applicable) and HDMI1 & 2 input.
Through the SCART1 & 2 connectors, a monitor output is
foreseen.

9.6.2

Additional LVDS Interface Panel (only for 19" and 20"
versions)

An additional LVDS Interface Panel acts as interface between
the SSB and the LCD panel. This is a buy-in panel and
therefore a black-box for Service.

9.7

Memory addressing

Figure “Memory block diagram” shows the interconnection
between the microprocessor, the FLASH memory, the Trident
Video Processor and the SDRAM.

Figure 9-8 Memory block diagram

Control signals CPU_RST, WR, RD and CE, address lines
A[0:19] and data lines D[0:7] are used for transferring data
between the microprocessor (item 7311) and the flash memory
(item 7310). Control signals CS, WR and RD, address lines
A[0:7] and data lines D[0:7] are used for transferring data
between the Trident Video Processor (item 7202) and the
microprocessor (item 7311). Control signals CX_BA0,
CX_BA1, CX_MCLK, CX_CLKE, CX_CS0, CX_RAS, CX_CAS
and CX_WE, address lines CX_MA[0:11] and data lines
DQ[0:15] are used for transferring data between the Trident
Video Processor and the SDRAM ICs (items 7204 and 7205).

9.8

Audio Processing

The audio decoding is done entirely via the Multistandard
Sound Processor (MSP) 4450P (item 7411).
This processor covers the processing of both analogue and
(NICAM) digital input signals by processing the (analogue) IF
signal-in to processed (analogue) AF-out (baseband audio). An
internal 40 ms (stereo) audio delay line (LIP SYNC) is foreseen
and therefore no external delay line is necessary.

All internal clock signals are derived from an external
18.432 MHz oscillator, which, in NICAM or I

S-mode, on its

turn is locked to the corresponding source.

The following functionality is included:
•

Automatic Standard Detection (ASD) automatically detects
the actual broadcasted TV standard

•

Automatic Sound Select (ASS) automatically switches
(without any I

C-bus action) between mono/stereo/

bilingual mode when the broadcast mode changes.

9.8.1

Audio Application

Figure 9-9 Block diagram audio processing - EU application

In EU applications, the MSP features:
•

Sound IF input for signals coming from the analogue
front-end

•

Three I

S-inputs for signals (“DATA”, “CLK” and “WS”)

coming from the MOJO in case of digital reception

•

Five analogue inputs: for EXT1 to EXT4 and HDMI

•

Loudspeaker output path

•

Headphone output path

•

SCART-1 output path (RF)

•

SCART-2 output path (WYSIWYG = monitor).

Digital audio signals coming from HDMI sources are fed to a
digital-to-analogue converter and then fed to the MSP.
In case of reception of digital TV signals, digital audio signals
coming from the MOJO are directly fed to the MSP via the
I2S_DA_IN1, I2S_WS1 and I2S_CL1 lines. This ensures a
“true digital path”.

The microprocessor (item 7311) controls the audio part with the
following control lines:
•

MUTEn: used to mute the Class D amplifiers

•

ANTI_PLOP: used to detect any DC failure in the Class D
amplifiers

•

DC_PROT: used to detect any DC failure in the Class D
amplifiers.

9.8.2

Audio Amplifier

The audio amplifier is an integrated class-D amplifier
(TDA8932T, item 7A01). It combines a good performance with
a high efficiency, resulting in a big reduction in heat generation.

7202

7204

7205

micro-

proce

1MB

h Memory

Trident CX

DRAM

CPU_R

T/WR/RD/CE

D[0:7]