SR200 MIL-STD Rugged Computer User’s Manual V1.0
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PCI Express Root Port6
control the PCI Express Root port, the options are enabled/disabled
ASPM Support: Set the ASPM Level: Force L0s – Force all links to L0s State: AUTO – BIOS auto configure:
DISABLE – Disables ASPM.
L1 Substates: PCI Express L1 Substates setting.
URR: Enable or disable PCI Express Unsupported Request Reporting.
FER: Enable or disable PCI Express Device Fatal Error Reporting.
NFER: Enable or disable PCI Express Device Non-Fatal Error Reporting.
CER: Enable or disable PCI Express Device Correctable Error Reporting.
CTO: Enable or disable PCI Express Completion Timer TO.
SEFE:
Enable or disable Root PCI Express System Error on Fatal Error.
SENFE: Enable or disable Root PCI Express System Error on Non-Fatal Error.
SECE: Enable or disable Root PCI Express System Error on Correctable Error.
PME SCI: Enable or disable PCI Express PME SCI.
Hot Plug: Enable or disable PCI Express Hot Plug.
PCIe Speed: Select PCI Express port speed.
Detect Non-Compliance Device: Detect Non-Compliance PCI Express Device. If enable, it will take more
time at POST time.
Extra Bus Reserved: Extra Bus Reserved (0-7) for bridges behind this Root Bridge.
Reseved Memory: Reserved Memory Range for this Root Bridge.
Prefetchable Memory: Prefetchable Memory Range for this Root Bridge.
Reserved I/O: Reserved I/O (4K/8K/12K/16K/…/48K) Range for this Root Bridge.
PCIE LTR: PCIE Latency Reporting Enable/Disable.
PCIE LTR Lock: PCIE LTR Configuration Lock.
Snoop Latency Ocerride: Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerride: Non Snoop Latency Ocerride for PCH PCIE.
