VMP2
Configuration
ID 24855, Rev. 02
Page 4 - 13
© 2002 PEP Modular Computers GmbH
4.3.4.6 Watchdog Control Register
The Watchdog Control register is the interface between applications and the operating
system for controlling the functioning of the Watchdog. Together with the Event Register,
bit 0 (WD) and bit 2 (PB2), the possibility is provided for either hardware (Abort switch)
or software (Watchdog timer) intervention in the execution of the application.
Table 4-11: Watchdog Control Register
REGISTER NAME
WATCHDOG CONTROL
ACCESS
ADDRESS
0xFFE0 0018
R
W
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LSB
CONTENT
WD_EN
WD_R WD_CCD WD_TRG
res.
res.
WDT1
WDT0
DEFAULT
0
0
0
0
n/a
n/a
n/a
n/a
BIT
NAME
VAL
DESCRIPTION
0
WDT0
0
Settings: WDT1 WDT0
0
0
0.5 seconds Watchdog timeout time
0
1
1.0 seconds Watchdog timeout time
1
0
1.5 seconds Watchdog timeout time
1
1
2.0 seconds Watchdog timeout time
1
1
WDT1
0
1
2
0
Reserved
1
3
0
Reserved
1
4
WD_TRG
0
When WD-EN (bit 7) set to 1, indicates that Watchdog timer has not been
retriggered.
1
Causes the Watchdog to be retriggered
(Resets Watchdog timer to value indicated by bits 0 and 1, and WD_TRG
(bit 4) to 0)
5
WD_CCD
0
Normal watchdog functionality
1
Cascade mode: when watchdog timout occurs, an NMI will be generated,
the watchdog timer resets, a further timeout will result in a system reset
6
WD_R
0
Causes hardware reset of system upon Watchdog timeout
1
Causes generation of a non-maskable interrupt upon Watchdog timeout
7
WD_EN
0
Watchdog timer disabled
1
Watchdog timer enabled
Note...
Once the Watchdog timer is enabled it
cannot be disabled except by resetting the
system.
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