Introduction
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7
1.4. BLOCK DIAGRAM
×
Figure 1.1
Ø
Pentium
P54CT
CACHE
SRAM
DRAM
Y2
Y3
HOST BUS
PCI BUS
EISA BUS
ISA SLOT
PCI SLOT
Address
Control
Data
Address/Data
Control
Address
Data
Control
#1
#2
#3
#1
#4
#2
#3
8042
BIOS
Clock
Clock A
Clock B
Clock D
Clock C
8 MHz Clock
Control
Data
Address
LBX
LBX
PCMC
SIO
Clock E
82378
82434
82433
60 MHz
14.318 MHz
CPU
#4
1.5. INTRODUCE THE PCI - BUS
Connecting devices to a CPU local bus can dramatically increase the speed of I/O-bound
peripherals with only a slight increase in cost over traditional systems. This
price / performance point has created a vast market potential for local bus products. The
main barrier to this market has been the lack of an accepted standard for local bus
peripherals. Many mainboard and chipset manufactures developed their own local bus
implementations, but they are incompatible with each other. The VL (Video Electronics
Standards Association) local bus and PCI (Peripheral Component Interconnect) bus
specification was created to end this confusion.
The PCI - bus standard, under development since Jun. 1992, which is designed to bring
workstation-level performance to standard PC platform. The PCI - bus removes many of the
bottlenecks that have hampered PC for several years. On the PCI - bus, peripherals operate
at the native speed of the computer system, thus enabling data transfer between peripherals
and the system at maximum speed. This performance is critical for bandwidth-constrained
devices such as video, multimedia, mass storage, and networking adapters.
