Page 24
Pentek Model 78661 Installation Manual
Rev.: 1.7
2.10
PCIe Carrier Connectors
(continued)
2.10.7
GPIO Connector (Option 104)
A 68−pin connector on the back edge of the 7806 PCB, labeled
J5
on the
PCB, provides I/O from the PMC
P14
connector, described in
Cables of various lengths with the mating connector are available: Pentek
Model 2147. The mating connector alone is Model 2147−999. The following
table identifies the 71661 FPGA LVDS signals on this connector.
Table 2
−
12: GPIO Connector Pins
PMC P14 Signal
Pin
Pin
PMC P14 Signal
GND
B1
A1
GND
P4_LVDS_OUT_N0
B2
A2
P4_LVDS_OUT_P0
P4_LVDS_IN_N0
B3
A3
P4_LVDS_IN_P0
P4_LVDS_OUT_N1
B4
A4
P4_LVDS_OUT_P1
P4_LVDS_IN_N1
B5
A5
P4_LVDS_IN_P1
P4_LVDS_OUT_N2
B6
A6
P4_LVDS_OUT_P2
P4_LVDS_IN_N2
B7
A7
P4_LVDS_IN_P2
P4_LVDS_OUT_N3
B8
A8
P4_LVDS_OUT_P3
P4_LVDS_IN_N3
B9
A9
P4_LVDS_IN_P3
P4_LVDS_OUT_N4
B10
A10
P4_LVDS_OUT_P4
P4_LVDS_IN_N4
B11
A11
P4_LVDS_IN_P4
P4_LVDS_OUT_N5
B12
A12
P4_LVDS_OUT_P5
P4_LVDS_IN_N5
B13
A13
P4_LVDS_IN_P5
P4_LVDS_OUT_N6
B14
A14
P4_LVDS_OUT_P6
P4_LVDS_IN_N6
B15
A15
P4_LVDS_IN_P6
P4_LVDS_OUT_N7
B16
A16
P4_LVDS_OUT_P7
P4_LVDS_IN_N7
B17
A17
P4_LVDS_IN_P7
P4_LVDS_OUT_N8
B18
A18
P4_LVDS_OUT_P8
P4_LVDS_IN_N8
B19
A19
P4_LVDS_IN_P8
P4_LVDS_OUT_CLK_N11
B20
A20
P4_LVDS_OUT_CLK_P11
P4_LVDS_IN_CLK_N11
B21
A21
P4_LVDS_IN_CLK_P11
No connect
B22
A22
No connect
B23
A23
B24
A24
B25
A25
B26
A26
B27
A27
B28
A28
B29
A29
B30
A30
B31
A31
B32
A32
B33
A33
GND
B34
A34
GND
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34