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2-5
180001UA
generate the receive clock provided to the V.35 interface. The external
transmit clock provided on the V.35 interface is used to generate the
transmit clock provided to the PCM channel. This mode is not available for
X.21.
Ext TX TIMING
D
T
E
TX BUFFER
RX BUFFER
TX DATA
RX TIMING
RX DATA
RX DATA
TX DATA
PCM
TX TIMING
RX TIMING
Mode 5 (SW4-5
OFF
OFF
OFF
OFF
OFF
1, 2, 3, 4
ON
ON
ON
ON
ON
)
The 2072 (CTS IC-G.703) gives both the receive and transmit clock to the
DTE connected on the V.35 interface. The receive clock provided on the
PCM channel is used to generate the receive clock provided to the V.35
interface. An internal time base is used to generate all transmit clocks.
This mode is not available for X.21.
TX TIMING
D
T
E
TX BUFFER
RX BUFFER
TX DATA
RX TIMING
RX DATA
RX DATA
TX DATA
PCM
RX TIMING
OSC.
TX TIMING
TX TIMING
Line Terminal Block
The terminal block on the rear panel of the 2072 (CTS IC-G.703) is used to
connect to the G.703 PCM system. The input from the G.703 system
connect to the terminals labeled RX. The output from the 2072 (CTS IC-
G.703) to the G.703 system come from the terminals labeled TX. Both
input and output are transformer coupled and are not polarity sensitive.
Factory Test Straps
The Factory Test Straps JP1, JP2 and JP3 must be installed for proper
operation of the interface converter.