Pantech PG-1810, Service Manual

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PG-1810 Service Manual
PANTECH R&D CONFIDENTIAL
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PG-1810’s Aero II transceiver uses a digital low-IF receiverar chitecture that allows for the on-chip
integration of the channel selection filters, eliminating the external RF image reject filters, and the IF
SAW filter required in conventional superheterodyne architectures. Compared with direct-conversion
architectures, the digital low-IF architecture has a much greater degree of immunity to dc offsets that
can arise from RF local oscillator (RFLO) self-mixing, second-order distortion of blockers (AM
suppression), and device 1/f noise.
The digital low-IF receiver's immunity to dc offsets has the benefit of expanding part selection and
improving manufacturing. At the front end, the common-mode balance requirements on the input SAW
filters are relaxed, and the PCB board design is simplified. At the radio's opposite end, the BBIC is one
of the handset's largest BOM contributors. It is not uncommon for a direct conversion solution to be
compatible only with a BBIC from the same supplier in order to address the complex dc offset issues.
However, since the Aero II transceiver has no requirement for BBIC support of complex dc offset
compensation, it is able to interface to all of the industry leading baseband ICs.
The receive (RX) section integrates four differentialinput low noise amplifiers (LNAs) supporting the
GSM 850 (869–894 MHz), E-GSM 900 (925–960 MHz), DCS 1800 (1805–1880 MHz), and PCS 1900
(1930– 1990 MHz) bands. The LNA inputs are matched to 150 or 200 Ω balanced-output SAW filters
through external LC matching networks. The active LNA input is automatically selected by the
ARFCN[9:0] bits and the BANDIND bit in Register 21h. If performing LNA swapping, the LNASWAP bit
in Register 05h is also needed. The LNA gain is controlled with the LNAG bit in Register 20h. A
quadrature image-reject mixer downconverts the RF signal to a low intermediate frequency (IF). The
mixer output is amplified with an analog programmable gain amplifier (PGA) that is controlled with the
AGAIN[2:0] bits in Register 20h. The quadrature IF signal is digitized with high resolution
analog-to-digital converters (ADCs).
The ADC output is downconverted to baseband with a digital quadrature local oscillator signal. Digital
decimation and FIR filters perform digital filtering, and remove ADC quantization noise, blockers, and
reference interferers. The response of the FIR filter is programmable to a flat passband setting
(FILTSEL = 0, Register 08h) and a linear phase setting (FILTSEL = 1, Register 08h). After filtering, the
digital output is scaled with a PGA, which is controlled with the DGAIN[5:0] bits in Register 20h.
The LNAG, AGAIN[2:0], and DGAIN[5:0] register bits should be set to provide a constant amplitude
signal to the baseband receive inputs.
Digital-to-analog converters (DACs) drive differential I and Q analog signals onto the BIP, BIN, BQP,
and BQN pins to interface to standard analog-input baseband ICs. The receive DACs are updated at
1.083 MHz and have a first-order reconstruction filter with a 1 MHz bandwidth. No special processing is
required in the baseband for dc offset compensation. The receive and transmit baseband I/Q pins are
multiplexed together in a 4-wire interface (BIP, BIN, BQP, and BQN). The common mode level at the
receive I and Q outputs is programmable with the DACCM[1:0] bits, and the fullscale level is
programmable with the DACFS[1:0] bits in Register 05h.