SCHEMATIC DIAGRAM-5
(8MBIT FLASH ROM)
IC7
C3FBLD000072
(DAC)
IC8
COFBBH00043
C46
6.3V47
C44
0.1P
R162
100
C42
+3.3D
+3.3A
6.3V47
C47
16N10
14
15
16
17
+3.3D
18
LRCK
B
C
A
SDAT
BCLK
VCC
Rch
GND
REF
Lch
+3.3D
RESET
RY/BY
CE
OE
WE
13
12
11
10
9
AD
8
7
6
5
4
3
2
1
0
14
15
13
12
11
10
9
8
7
DT
6
5
4
3
2
1
0
C40
0.1P
VCC
23
BYTE
33
VSS
23
VSS
33
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
1
44
2
3
12
14
43
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
A
B
A
B
C
D
E
F
G
K
L
M
N
O
P
Q
C
N
O
P
F
G
H
I
J
R24
47K
R25
47K
R53
47K
7
5
6
M5218FPE3
IC10B
2SJ106YTE85R
Q10
4.7K
R19
15K
R55
0.1P
C114
(OP.AMP)
7
5
6
M5218FPE3
IC9B
(OP.AMP)
R64
150
R175
2.2K
R172
150
R176
2.2K
R174
220K
C51
22P
4
8
VCC
GND
M5218FPE3
+15A
(OP.AMP)
-15A
M5218FPE3
+5
+15A
IC17B
(OP.AMP)
C111
0.1P
1
3
2
M5218FPE3
IC17A
(OP.AMP)
7
5
6
C110
0.1P
CN2
HPS
-15A
+15A
+15HM
Rch
MIXR
Lch
MIXL
HPS
+15A
-15A
E
SELL
SELR
A
UXR
A
UXL
G-IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+15HM
33K
R169
4.7K
R21
100K
R171
4.7K
R20
82K
R170
2SJ106YTE85R
Q11
2SJ106YTE85R
Q12
2SJ106YTE85R
Q6
4.7K
R16
R173
220K
C48
22P
33K
R166
4.7K
R18
100K
R168
4.7K
R17
82K
R167
2SJ106YTE85R
Q8
2SJ106YTE85R
Q9
15K
R54
15K
R48
0.1P
C112
0.1P
C113
5
6
7
8
4
3
2
1
C45
16N10
R52
220
C41
2200
R41
22K
R44
22K
R46
22K
N
N
SY-PA100
MAIN SCHEMATIC DIAGRAM
4
5
3
TO CPR/MIX CIRCUIT
(CN2) ON SCHEMATIC DIAGRAM 13
0.1
C117
E1
0.1
C116
E2
0.1
C115
E3
0.1
C30
Summary of Contents for SY-PA100
Page 24: ...24...
Page 25: ...12 MEASURING CONDITION 12 1 Measuring condition of MAIN P C B Check Point 1 9 25...
Page 45: ...45...
Page 46: ...19 PACKAGING 46...